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zephyr/soc/arm/xilinx_zynqmp/linker.ld

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soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
/*
* Copyright (c) 2019 Lexmark International, Inc.
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
*
* SPDX-License-Identifier: Apache-2.0
*/
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
#include <autoconf.h>
#if defined(CONFIG_SOC_XILINX_ZYNQMP_RPU)
arch: arm: aarch32: Rename `cortex_r` to `cortex_a_r` This commit renames the `cortex_r` directory under the AArch32 to `cortex_a_r`, in preparation for the AArch32 Cortex-A support. The rationale for this renaming is that the Cortex-A and Cortex-R share the same base design and the difference between them, other than the MPU vs. MMU, is minimal. Since most of the architecture port code and configurations will be shared between the Cortex-A and Cortex-R architectures, it is advantageous to have them together in the same directory. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-03-22 22:19:22 +08:00
#include <arch/arm/aarch32/cortex_a_r/scripts/linker.ld>
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
#endif