OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/soc/arm/xilinx_zynqmp/Kconfig.defconfig

32 lines
719 B
Plaintext
Raw Normal View History

soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
# Copyright (c) 2019 Lexmark International, Inc.
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
# SPDX-License-Identifier: Apache-2.0
if SOC_XILINX_ZYNQMP
config SOC
default "xilinx_zynqmp"
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
if SOC_XILINX_ZYNQMP_RPU
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
config NUM_IRQS
# must be >= the highest interrupt number used
# - include the UART interrupts
default 220
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 12000000
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
endif # SOC_XILINX_ZYNQMP_RPU
kconfig: Convert device tree chosen properties to new kconfigfunctions Convert how we get the various chosen properties like "zephyr,console" to use the new kconfig functions like dt_chosen_to_label. Because of how kconfig parses things we define a set of variables of the form DT_CHOSEN_Z_<PROP> since comma's are parsed as field seperators in macros. This conversion allows us to remove code in gen_defines.py for the following chosen properties: zephyr,console zephyr,shell-uart zephyr,bt-uart zephyr,uart-pipe zephyr,bt-mon-uart zephyr,uart-mcumgr zephyr,bt-c2h-uart Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-08-28 22:29:26 +08:00
# Workaround for not being able to have commas in macro arguments
DT_CHOSEN_Z_FLASH := zephyr,flash
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
config FLASH_SIZE
kconfig: Introduce typed dt kconfig functions Replace: dt_chosen_reg_addr dt_chosen_reg_size dt_node_reg_addr dt_node_reg_size with: dt_chosen_reg_addr_int dt_chosen_reg_size_int dt_chosen_reg_addr_hex dt_chosen_reg_size_hex dt_node_reg_addr_int dt_node_reg_size_int dt_node_reg_addr_hex dt_node_reg_size_hex So that we get the proper formatted string for the type of symbol. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-10-24 04:15:59 +08:00
default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
config FLASH_BASE_ADDRESS
kconfig: Introduce typed dt kconfig functions Replace: dt_chosen_reg_addr dt_chosen_reg_size dt_node_reg_addr dt_node_reg_size with: dt_chosen_reg_addr_int dt_chosen_reg_size_int dt_chosen_reg_addr_hex dt_chosen_reg_size_hex dt_node_reg_addr_int dt_node_reg_size_int dt_node_reg_addr_hex dt_node_reg_size_hex So that we get the proper formatted string for the type of symbol. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-10-24 04:15:59 +08:00
default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
soc: arm: xilinx_zynqmp: Add qemu based SoC This commit adds support for the Zynq UltraScale+ MPSoC as a qemu based platform for Cortex-R based testing. This SoC only supports an interrupt controller and serial port for limited testing. Signed-off-by: Bradley Bolen <bbolen@lexmark.com>
2019-07-22 22:23:47 +08:00
soc: arm: xilinx_zynqmp: Refactor for multi-arch support. The Xilinx ZynqMP SoC embeds both Cortex-R "RPU" and Cortex-A "APU" cores. Since the current Zephyr architecture cannot support AMP of Cortex-R and Cortex-A within the same project, the RPU and APU should be considered separate platforms and handled accordingly. This commit re-purposes the SOC_XILINX_ZYNQMP symbol as a helper symbol indicating that Xilinx ZynqMP SoC is used, and adds a new symbol, SOC_XILINX_ZYNQMP_RPU, for specifying the actual build target platform. When Cortex-A support is added in the future, SOC_XILINX_ZYNQMP_APU symbol should be added and used to conditionally handle APU-specific code. For more details, refer to the issue #20217. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2019-11-01 02:19:54 +08:00
endif # SOC_XILINX_ZYNQMP