207 lines
7.7 KiB
C
207 lines
7.7 KiB
C
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nordic_nrf_can
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#include <stdint.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/can.h>
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#include <zephyr/drivers/can/can_mcan.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/irq.h>
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/* nRF CAN wrapper offsets */
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#define CAN_TASKS_START offsetof(NRF_CAN_Type, TASKS_START)
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#define CAN_EVENTS_CORE_0 offsetof(NRF_CAN_Type, EVENTS_CORE[0])
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#define CAN_EVENTS_CORE_1 offsetof(NRF_CAN_Type, EVENTS_CORE[1])
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#define CAN_INTEN offsetof(NRF_CAN_Type, INTEN)
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struct can_nrf_config {
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uint32_t wrapper;
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uint32_t mcan;
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uint32_t mrba;
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uint32_t mram;
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const struct device *clock;
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const struct pinctrl_dev_config *pcfg;
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void (*irq_configure)(void);
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uint16_t irq;
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};
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static void can_nrf_irq_handler(const struct device *dev)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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if (sys_read32(config->wrapper + CAN_EVENTS_CORE_0) == 1U) {
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sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0);
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can_mcan_line_0_isr(dev);
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}
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if (sys_read32(config->wrapper + CAN_EVENTS_CORE_1) == 1U) {
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sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1);
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can_mcan_line_1_isr(dev);
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}
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}
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static int can_nrf_get_core_clock(const struct device *dev, uint32_t *rate)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return clock_control_get_rate(config->clock, NULL, rate);
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}
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static const struct can_driver_api can_nrf_api = {
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.get_capabilities = can_mcan_get_capabilities,
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.start = can_mcan_start,
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.stop = can_mcan_stop,
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.set_mode = can_mcan_set_mode,
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.set_timing = can_mcan_set_timing,
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.send = can_mcan_send,
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.add_rx_filter = can_mcan_add_rx_filter,
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.remove_rx_filter = can_mcan_remove_rx_filter,
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.get_state = can_mcan_get_state,
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#ifdef CONFIG_CAN_MANUAL_RECOVERY_MODE
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.recover = can_mcan_recover,
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#endif /* CONFIG_CAN_MANUAL_RECOVERY_MODE */
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.get_core_clock = can_nrf_get_core_clock,
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.get_max_filters = can_mcan_get_max_filters,
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.set_state_change_callback = can_mcan_set_state_change_callback,
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.timing_min = CAN_MCAN_TIMING_MIN_INITIALIZER,
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.timing_max = CAN_MCAN_TIMING_MAX_INITIALIZER,
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#ifdef CONFIG_CAN_FD_MODE
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.set_timing_data = can_mcan_set_timing_data,
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.timing_data_min = CAN_MCAN_TIMING_DATA_MIN_INITIALIZER,
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.timing_data_max = CAN_MCAN_TIMING_DATA_MAX_INITIALIZER,
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#endif /* CONFIG_CAN_FD_MODE */
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};
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static int can_nrf_read_reg(const struct device *dev, uint16_t reg, uint32_t *val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return can_mcan_sys_read_reg(config->mcan, reg, val);
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}
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static int can_nrf_write_reg(const struct device *dev, uint16_t reg, uint32_t val)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return can_mcan_sys_write_reg(config->mcan, reg, val);
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}
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static int can_nrf_read_mram(const struct device *dev, uint16_t offset, void *dst, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return can_mcan_sys_read_mram(config->mram, offset, dst, len);
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}
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static int can_nrf_write_mram(const struct device *dev, uint16_t offset, const void *src,
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size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return can_mcan_sys_write_mram(config->mram, offset, src, len);
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}
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static int can_nrf_clear_mram(const struct device *dev, uint16_t offset, size_t len)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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return can_mcan_sys_clear_mram(config->mram, offset, len);
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}
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static const struct can_mcan_ops can_mcan_nrf_ops = {
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.read_reg = can_nrf_read_reg,
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.write_reg = can_nrf_write_reg,
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.read_mram = can_nrf_read_mram,
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.write_mram = can_nrf_write_mram,
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.clear_mram = can_nrf_clear_mram,
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};
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static int can_nrf_init(const struct device *dev)
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{
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const struct can_mcan_config *mcan_config = dev->config;
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const struct can_nrf_config *config = mcan_config->custom;
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int ret;
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if (!device_is_ready(config->clock)) {
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return -ENODEV;
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}
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ret = clock_control_on(config->clock, NULL);
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if (ret < 0) {
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return ret;
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}
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ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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return ret;
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}
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sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_0);
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sys_write32(0U, config->wrapper + CAN_EVENTS_CORE_1);
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sys_write32(CAN_INTEN_CORE0_Msk | CAN_INTEN_CORE1_Msk, config->wrapper + CAN_INTEN);
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sys_write32(1U, config->wrapper + CAN_TASKS_START);
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config->irq_configure();
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ret = can_mcan_configure_mram(dev, config->mrba, config->mram);
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if (ret < 0) {
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return ret;
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}
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ret = can_mcan_init(dev);
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if (ret < 0) {
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return ret;
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}
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return 0;
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}
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#define CAN_NRF_DEFINE(n) \
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static inline void can_nrf_irq_configure##n(void) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), DT_INST_IRQ(n, priority), can_nrf_irq_handler, \
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DEVICE_DT_INST_GET(n), 0); \
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irq_enable(DT_INST_IRQN(n)); \
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} \
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\
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static const struct can_nrf_config can_nrf_config##n = { \
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.wrapper = DT_INST_REG_ADDR_BY_NAME(n, wrapper), \
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.mcan = CAN_MCAN_DT_INST_MCAN_ADDR(n), \
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.mrba = CAN_MCAN_DT_INST_MRBA(n), \
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.mram = CAN_MCAN_DT_INST_MRAM_ADDR(n), \
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.clock = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.irq = DT_INST_IRQN(n), \
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.irq_configure = can_nrf_irq_configure##n, \
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}; \
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\
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CAN_MCAN_DT_INST_CALLBACKS_DEFINE(n, can_mcan_nrf_cbs##n); \
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\
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static const struct can_mcan_config can_mcan_nrf_config##n = CAN_MCAN_DT_CONFIG_INST_GET( \
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n, &can_nrf_config##n, &can_mcan_nrf_ops, &can_mcan_nrf_cbs##n); \
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\
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static struct can_mcan_data can_mcan_nrf_data##n = CAN_MCAN_DATA_INITIALIZER(NULL); \
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\
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DEVICE_DT_INST_DEFINE(n, can_nrf_init, NULL, &can_mcan_nrf_data##n, \
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&can_mcan_nrf_config##n, POST_KERNEL, CONFIG_CAN_INIT_PRIORITY, \
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&can_nrf_api);
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DT_INST_FOREACH_STATUS_OKAY(CAN_NRF_DEFINE)
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