2015-09-20 11:49:34 +08:00
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/*
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* Copyright (c) 2013-2015, Wind River Systems, Inc.
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*
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2015-10-07 00:00:37 +08:00
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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2015-09-20 11:49:34 +08:00
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*
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2015-10-07 00:00:37 +08:00
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* http://www.apache.org/licenses/LICENSE-2.0
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2015-09-20 11:49:34 +08:00
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*
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2015-10-07 00:00:37 +08:00
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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2015-09-20 11:49:34 +08:00
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*/
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2015-12-04 23:09:39 +08:00
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/**
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* @file
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* @brief System/hardware module for the galileo platform
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*
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2015-10-21 00:42:33 +08:00
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* This module provides routines to initialize and support board-level hardware
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* for the galileo platform.
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*
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* Implementation Remarks:
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* Handlers for the secondary serial port have not been added.
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2015-09-20 11:49:34 +08:00
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*/
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#include <nanokernel.h>
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#include <init.h>
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#include <device.h>
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#include <misc/printk.h>
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#include <misc/__assert.h>
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2015-12-17 21:54:35 +08:00
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#include "soc.h"
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2015-10-15 14:48:03 +08:00
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#include <uart.h>
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2015-09-20 11:49:34 +08:00
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#include <drivers/pci/pci.h>
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#include <drivers/pci/pci_mgr.h>
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#include <drivers/ioapic.h>
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2015-09-24 05:03:52 +08:00
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#ifdef CONFIG_PCI_LEGACY_BRIDGE
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/**
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*
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* @brief Configure PCI interrupt pin to IRQ mapping
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*
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* The routine detects PCI legacy bridge and if present,
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* configures PCI interrupt pin to IRQ mapping for D:20
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* and D:21 IO Fabric, that contains the following devices:
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* - SPI0, SPI1;
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* - I2C;
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* - GPIO;
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* - UART0, UART1;
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* - SDIO/eMMC, USB, Ethernet.
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*/
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static int pci_legacy_bridge_irq_config(struct device *unused)
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{
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ARG_UNUSED(unused);
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struct pci_dev_info info = {
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.function = PCI_FUNCTION_ANY,
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.bar = PCI_BAR_ANY,
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};
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if (pci_legacy_bridge_detect(&info) == 0) {
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pci_legacy_bridge_configure(&info, 1, PCI_INTA, 16);
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pci_legacy_bridge_configure(&info, 1, PCI_INTB, 17);
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pci_legacy_bridge_configure(&info, 1, PCI_INTC, 18);
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pci_legacy_bridge_configure(&info, 1, PCI_INTD, 19);
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2016-01-29 03:50:59 +08:00
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pci_legacy_bridge_configure(&info, 0, PCI_INTA, 17);
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pci_legacy_bridge_configure(&info, 0, PCI_INTB, 18);
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pci_legacy_bridge_configure(&info, 0, PCI_INTC, 19);
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pci_legacy_bridge_configure(&info, 0, PCI_INTD, 16);
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2015-09-24 05:03:52 +08:00
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}
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return 0;
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}
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2016-01-29 04:16:31 +08:00
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SYS_INIT(pci_legacy_bridge_irq_config,
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SECONDARY, CONFIG_KERNEL_INIT_PRIORITY_DEVICE);
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2015-09-24 05:03:52 +08:00
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#endif /* CONFIG_PCI_LEGACY_BRIDGE */
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