2016-11-08 23:36:50 +08:00
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/*
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* Copyright (c) 2013-2016 Wind River Systems, Inc.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/**
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* @file
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* @brief Private kernel definitions (ARM)
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*
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* This file contains private kernel function definitions and various
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* other definitions for the ARM Cortex-M3 processor architecture.
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*
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* This file is also included by assembly language files which must #define
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* _ASMLANGUAGE before including this header file. Note that kernel
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* assembly source files obtains structure offset values via "absolute symbols"
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* in the offsets.o module.
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*/
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/* this file is only meant to be included by kernel_structs.h */
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#ifndef _kernel_arch_func__h_
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#define _kernel_arch_func__h_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef _ASMLANGUAGE
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extern void _FaultInit(void);
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extern void _CpuIdleInit(void);
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static ALWAYS_INLINE void nanoArchInit(void)
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{
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_InterruptStackSetup();
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_ExcSetup();
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_FaultInit();
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_CpuIdleInit();
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}
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2016-11-21 00:08:53 +08:00
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static ALWAYS_INLINE void
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_arch_switch_to_main_thread(char *main_stack, size_t main_stack_size,
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_thread_entry_t _main)
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{
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/* get high address of the stack, i.e. its start (stack grows down) */
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char *start_of_main_stack;
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start_of_main_stack = main_stack + main_stack_size;
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start_of_main_stack = (void *)STACK_ROUND_DOWN(start_of_main_stack);
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_current = (void *)main_stack;
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kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.
However, this caused two problems:
1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.
2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.
To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.
On the ARM FRDM K64F board, this improvement is seen:
Before:
1- Measure time to switch from ISR back to interrupted task
switching time is 215 tcs = 1791 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 315 tcs = 2625 nsec
After:
1- Measure time to switch from ISR back to interrupted task
switching time is 130 tcs = 1083 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 225 tcs = 1875 nsec
These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.
Fixes ZEP-1401.
Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-02 23:37:27 +08:00
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/* the ready queue cache already contains the main thread */
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2016-11-21 00:08:53 +08:00
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__asm__ __volatile__(
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/* move to main() thread stack */
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"msr PSP, %0 \t\n"
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/* unlock interrupts */
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#ifdef CONFIG_CPU_CORTEX_M0_M0PLUS
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"cpsie i \t\n"
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#else
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"movs %%r1, #0 \n\t"
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"msr BASEPRI, %%r1 \n\t"
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#endif
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/* branch to _thread_entry(_main, 0, 0, 0) */
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"mov %%r0, %1 \n\t"
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"bx %2 \t\n"
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/* never gets here */
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:
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: "r"(start_of_main_stack),
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"r"(_main), "r"(_thread_entry)
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: "r0", "r1", "sp"
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);
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CODE_UNREACHABLE;
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}
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2016-11-08 23:36:50 +08:00
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static ALWAYS_INLINE void
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_set_thread_return_value(struct k_thread *thread, unsigned int value)
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{
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kernel/arm: fix race condition when setting _Swap() return value
There was a possible race condition when setting the return value of a
thread that is pending, from an ISR.
A kernel function causes a thread to pend, with the following series of
steps:
- disable interrupts
- move current thread to wait_q
- call _Swap
Depending if running on M3/4 or M0+, _Swap will either issue a svc #0,
or pend PendSV directly. The same problem exists in both cases.
M3/4:
__svc will:
- enable interrupts
- trigger __pendsv
M0+:
_Swap() will enable interrupts.
__pendsv will:
- save register context including PSP into the thread struct
If an interrupt occurs between interrupts being enabled them and
__pendsv saving PSP, and the ISR sets the pending thread's return value,
this will happen:
- sees the thread in a wait_q
- removes it
- makes it ready
- calls _set_thread_return_value
- _set_thread_return_value looks at the thread's saved PSP to poke
the value
In this scenario, PSP hasn't yet been updated by __pendsv so it's a
stale value from the previous context switch, resulting in unpredictable
word on the stack getting set to the return value.
There is no way to fix this issue and still have the return value being
delivered directly in the pending thread's exception stack frame, in the
M0+ case. There will always be a window between the unlocking of
interrupts and PendSV being handled. On M3/4, it could be possible with
the mix of SVC and PendSV, since the exception stack frame is created in
the __svc handler. However, because we want to keep the two
implementations as close as possible, and there were talks of moving
M3/4 to using PendSV only, to save an exception, the approach taken
solves both cases.
The approach taken is similar to the ARC and Nios2 ports, where
there is a field in the thread structure that holds the return value.
_Swap() then loads r0/a1 with that value just before returning.
Fixes ZEP-1289.
Change-Id: Iee7e06fe3f8ded84aff918fd43408c7f589344d9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-16 07:45:43 +08:00
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thread->arch.swap_return_value = value;
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2016-11-08 23:36:50 +08:00
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}
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extern void nano_cpu_atomic_idle(unsigned int);
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#define _is_in_isr() _IsInIsr()
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extern void _IntLibInit(void);
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#endif /* _ASMLANGUAGE */
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#ifdef __cplusplus
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}
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#endif
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#endif /* _kernel_arch_func__h_ */
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