zephyr/soc/arm/nordic_nrf/nrf53/Kconfig.series

# Nordic Semiconductor nRF53 MCU line

# Copyright (c) 2019 Nordic Semiconductor ASA
# SPDX-License-Identifier: Apache-2.0

config SOC_SERIES_NRF53X
	bool "Nordic Semiconductor nRF53 series MCU"
	select CPU_CORTEX_M33
	select CPU_CORTEX_M_HAS_DWT
	select CPU_HAS_ARM_MPU
	select SOC_FAMILY_NRF
	select XIP
	select HAS_NRFX
	select HAS_SEGGER_RTT
	help
	 Enable support for NRF53 MCU series
soc: arm: nrf53: add nRF5340 CPUAPP SoC definition Nordic nRF5340 CPUAPP (Application MCU) SoC definition (Secure and Non-Secure domains). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no> 2019-08-02 02:47:31 +08:00			`# Nordic Semiconductor nRF53 MCU line`

			`# Copyright (c) 2019 Nordic Semiconductor ASA`
			`# SPDX-License-Identifier: Apache-2.0`

			`config SOC_SERIES_NRF53X`
			`bool "Nordic Semiconductor nRF53 series MCU"`
			`select CPU_CORTEX_M33`
soc: arm: nordic_nrf: Select CPU DWT feature symbol The Data Watchpoint and Trace (DWT) is an optional debug unit for the Cortex-M family cores (except ARMv6-M; i.e. M0 and M0+) that provides watchpoints, data tracing and system profiling capabilities. Signed-off-by: Stephanos Ioannidis <root@stephanos.io> 2020-01-10 09:49:41 +08:00			`select CPU_CORTEX_M_HAS_DWT`
soc: arm: nrf53: add nRF5340 CPUAPP SoC definition Nordic nRF5340 CPUAPP (Application MCU) SoC definition (Secure and Non-Secure domains). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no> 2019-08-02 02:47:31 +08:00			`select CPU_HAS_ARM_MPU`
			`select SOC_FAMILY_NRF`
			`select XIP`
			`select HAS_NRFX`
			`select HAS_SEGGER_RTT`
			`help`
			`Enable support for NRF53 MCU series`