2019-11-01 20:45:29 +08:00
|
|
|
# STM32F0 and STM32F3 PLL configuration options
|
|
|
|
|
2019-05-28 21:49:05 +08:00
|
|
|
# Copyright (c) 2019 Linaro
|
2019-11-01 20:45:29 +08:00
|
|
|
# SPDX-License-Identifier: Apache-2.0
|
2019-05-28 21:49:05 +08:00
|
|
|
|
|
|
|
if SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
|
|
|
|
|
|
|
|
config CLOCK_STM32_PLL_PREDIV
|
|
|
|
int "PREDIV Prescaler"
|
2020-06-08 04:21:40 +08:00
|
|
|
depends on CLOCK_STM32_SYSCLK_SRC_PLL
|
2019-05-28 21:49:05 +08:00
|
|
|
default 1
|
|
|
|
range 1 16
|
|
|
|
help
|
2020-06-08 04:21:40 +08:00
|
|
|
PREDIV is a PLL clock signal prescaler for the HSE output.
|
|
|
|
It is supported by those parts that do not support PREDIV1.
|
|
|
|
If configured on a non-supported part, this config will be ignored.
|
|
|
|
Allowed values: 1 - 16.
|
2019-05-28 21:49:05 +08:00
|
|
|
|
|
|
|
config CLOCK_STM32_PLL_PREDIV1
|
|
|
|
int "PREDIV1 Prescaler"
|
2020-06-08 04:21:40 +08:00
|
|
|
depends on CLOCK_STM32_SYSCLK_SRC_PLL
|
2019-05-28 21:49:05 +08:00
|
|
|
default 1
|
|
|
|
range 1 16
|
|
|
|
help
|
2020-06-08 04:21:40 +08:00
|
|
|
PREDIV1 is a PLL clock signal prescaler for any PLL input.
|
|
|
|
It is supported by STM32F04xx, STM32F07xx, STM32F09xx, STM32F030xC,
|
|
|
|
STM32F302xE, STM32F303xE and STM32F39xx parts.
|
|
|
|
If configured on a non-supported part, this config will be ignored.
|
2019-11-01 17:24:07 +08:00
|
|
|
Allowed values: 1 - 16.
|
2019-05-28 21:49:05 +08:00
|
|
|
|
|
|
|
config CLOCK_STM32_PLL_MULTIPLIER
|
|
|
|
int "PLL multiplier"
|
|
|
|
depends on CLOCK_STM32_SYSCLK_SRC_PLL
|
|
|
|
default 6
|
|
|
|
range 2 16
|
|
|
|
help
|
2020-06-08 04:21:40 +08:00
|
|
|
PLL multiplier, allowed values: 2-16.
|
|
|
|
PLL output must not exceed 48MHz for STM32F0 series
|
|
|
|
or 72MHz for STM32F3 series.
|
2019-05-28 21:49:05 +08:00
|
|
|
|
|
|
|
endif # SOC_SERIES_STM32F0X || SOC_SERIES_STM32F3X
|