2024-03-06 06:45:15 +08:00
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# Copyright 2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_MCXNX4X
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select HAS_MCUX
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select HAS_MCUX_FLEXCOMM
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select CPU_CORTEX_M_HAS_SYSTICK
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select CPU_CORTEX_M_HAS_DWT
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select PLATFORM_SPECIFIC_INIT
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config SOC_MCXN947_CPU0
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select CPU_CORTEX_M33
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARM_TRUSTZONE_M
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select HAS_MCUX_CACHE
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if SOC_SERIES_MCXNX4X
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config SECOND_CORE_MCUX
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bool "MCXN94X's second core"
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depends on HAS_MCUX
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help
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Indicates the second core will be enabled, and the part will run
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in dual core mode.
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config FLASH_DISABLE_CACHE64
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bool "Disable the CACHE64 cache for FlexSPI flash accesses"
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help
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Disable cache64 cache.
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config MCUX_CORE_SUFFIX
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default "_cm33_core0" if SOC_MCXN947_CPU0
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default "_cm33_core1" if SOC_MCXN947_CPU1
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2024-03-20 03:48:19 +08:00
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DT_CHOSEN_Z_FLASH := zephyr,flash
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DT_COMPAT_FLEXSPI := nxp,imx-flexspi
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DT_CHOSEN_FLASH_NODE := $(dt_chosen_path,$(DT_CHOSEN_Z_FLASH))
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DT_CHOSEN_FLASH_PARENT := $(dt_node_parent,$(DT_CHOSEN_FLASH_NODE))
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DT_FLASH_PARENT_IS_FLEXSPI := $(dt_node_has_compat,$(DT_CHOSEN_FLASH_PARENT),$(DT_COMPAT_FLEXSPI))
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DT_FLASH_HAS_SIZE_PROP := $(dt_node_has_prop,$(DT_CHOSEN_FLASH_NODE),size)
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config FLASH_BASE_ADDRESS
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default $(dt_node_reg_addr_hex,$(DT_CHOSEN_FLASH_PARENT),1) \
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if $(DT_FLASH_PARENT_IS_FLEXSPI)
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config FLASH_SIZE
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default $(dt_node_int_prop_int,$(DT_CHOSEN_FLASH_NODE),size,Kb) \
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if $(DT_FLASH_HAS_SIZE_PROP)
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config FLASH_MCUX_FLEXSPI_XIP
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bool
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default $(DT_FLASH_PARENT_IS_FLEXSPI)
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select XIP
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help
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Allows for the soc to safely initialize the clocks for the
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FlexSpi when planning to execute code in FlexSpi Memory.
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2024-03-06 06:45:15 +08:00
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endif # SOC_SERIES_MCXNX4X
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