2020-10-23 18:01:18 +08:00
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/*
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* Copyright (c) 2020 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_
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#define ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/pcie/pcie.h>
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2022-12-07 06:09:44 +08:00
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#ifdef CONFIG_IVSHMEM_DOORBELL
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2022-05-06 16:25:46 +08:00
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#include <zephyr/drivers/pcie/msi.h>
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2022-12-07 06:09:44 +08:00
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#endif
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2020-11-24 17:11:23 +08:00
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2020-10-23 18:01:18 +08:00
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#define IVSHMEM_PCIE_REG_BAR_IDX 0
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2020-11-24 17:11:23 +08:00
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#define IVSHMEM_PCIE_SHMEM_BAR_IDX 2
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2020-10-23 18:01:18 +08:00
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2020-11-24 17:11:23 +08:00
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struct ivshmem_param {
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const struct device *dev;
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struct k_poll_signal *signal;
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uint8_t vector;
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};
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2020-10-23 18:01:18 +08:00
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struct ivshmem {
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DEVICE_MMIO_RAM;
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2022-11-11 19:15:55 +08:00
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struct pcie_dev *pcie;
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2020-10-23 18:01:18 +08:00
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uintptr_t shmem;
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size_t size;
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2020-11-24 17:11:23 +08:00
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#ifdef CONFIG_IVSHMEM_DOORBELL
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msi_vector_t vectors[CONFIG_IVSHMEM_MSI_X_VECTORS];
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struct ivshmem_param params[CONFIG_IVSHMEM_MSI_X_VECTORS];
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uint16_t n_vectors;
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#endif
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2020-10-23 18:01:18 +08:00
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};
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2020-11-24 17:11:23 +08:00
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struct ivshmem_reg {
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uint32_t int_mask;
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uint32_t int_status;
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uint32_t iv_position;
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uint32_t doorbell;
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};
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#define IVSHMEM_GEN_DOORBELL(i, v) ((i << 16) | (v & 0xFFFF))
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2020-10-23 18:01:18 +08:00
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#endif /* ZEPHYR_DRIVERS_VIRTUALIZATION_VIRT_IVSHMEM_H_ */
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