zephyr/soc/neorv32/soc.c

/*
 * Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>
 *
 * SPDX-License-Identifier: Apache-2.0
 */

#include <zephyr/irq.h>
#include <soc.h>

#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)
void soc_interrupt_init(void)
{
	(void)arch_irq_lock();

	csr_write(mie, 0);
}
#endif
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> 2021-08-15 05:52:35 +08:00			`/*`
			`* Copyright (c) 2021 Henrik Brix Andersen <henrik@brixandersen.dk>`
			`*`
			`* SPDX-License-Identifier: Apache-2.0`
			`*/`

soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> 2022-05-06 17:11:04 +08:00			`#include <zephyr/irq.h>`
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> 2021-08-15 05:52:35 +08:00			`#include <soc.h>`

			`#if defined(CONFIG_RISCV_SOC_INTERRUPT_INIT)`
			`void soc_interrupt_init(void)`
			`{`
arch/riscv: Boot secondary CPUs for SMP support Secondary CPUs are now initialised and made available to the system. If the system has more CPUs than configured via CONFIG_MP_NUM_CPUS, those are still left looping as before. Some implementations of `soc_interrupt_init` also changed to use `arch_irq_lock` instead of `irq_lock`. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com> 2021-12-30 02:22:48 +08:00			`(void)arch_irq_lock();`
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> 2021-08-15 05:52:35 +08:00
riscv: refactor: Utilize the available helper macro use helper macros from csr.h instead of inline assembly which results in cleaner and more maintainable code Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com> 2023-03-17 01:28:45 +08:00			`csr_write(mie, 0);`
soc: riscv: privilege: add neorv32 processor suppport Add support for the open-source NEORV32 RISC-V compatible processor system (SoC). Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk> 2021-08-15 05:52:35 +08:00			`}`
			`#endif`