zephyr/soc/gd/gd32/gd32f4xx/Kconfig.defconfig.gd32f405

# Copyright (c) 2021 BrainCo Inc.
# SPDX-License-Identifier: Apache-2.0

if SOC_GD32F405

config SYS_CLOCK_HW_CYCLES_PER_SEC
	default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)

config NUM_IRQS
	default 82

endif # SOC_GD32F405
soc: arm: gigadevice: support gd32f405xx soc Add support for GD32F405xx series SOCs. Signed-off-by: HaiLong Yang <cameledyang@pm.me> 2021-11-19 11:46:56 +08:00			`# Copyright (c) 2021 BrainCo Inc.`
			`# SPDX-License-Identifier: Apache-2.0`

soc: arm: fix gd32f4xx series config This add soc check for series config, also fix a miss spelling issue. Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn> 2022-07-21 23:24:39 +08:00			`if SOC_GD32F405`

soc: arm: gigadevice: support gd32f405xx soc Add support for GD32F405xx series SOCs. Signed-off-by: HaiLong Yang <cameledyang@pm.me> 2021-11-19 11:46:56 +08:00			`config SYS_CLOCK_HW_CYCLES_PER_SEC`
			`default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)`

			`config NUM_IRQS`
			`default 82`
soc: arm: fix gd32f4xx series config This add soc check for series config, also fix a miss spelling issue. Signed-off-by: HaiLong Yang <hailong.yang@brainco.cn> 2022-07-21 23:24:39 +08:00
			`endif # SOC_GD32F405`