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zephyr/soc/arm/ti_simplelink/cc32xx/soc.h

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cc3200: Add support for the TI CC32xx SoC Series Initial support is for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3200 SDK driver peripheral library, installed separately, or built from ext/hal/. Jira: ZEP-1109 Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-10-26 07:49:35 +08:00
/*
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with the NWP interrupt number of 171 caused a hard fault during a subsequent svc #0 instruction during _Swap(). GNU compiler is generating a bit extension instruction (sxtb) which converts a positive IRQ value argument to a negative value when casting to the CMSIS IRQn_Type enum parameter type. This generates a negative index, which then writes to an SCB control register instead of NVIC register, causing a hard fault later on. This issue only occurs when passing interrupt numbers > 0x80 (eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis. The solution here is simply to redefine IRQn_Type to be an unsigned 32 bit integer, while redefining the CMSIS IRQn_Type enum definitions for interrupts less than zero. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-06-03 08:16:43 +08:00
* Copyright (c) 2016-2017, Texas Instruments Incorporated
cc3200: Add support for the TI CC32xx SoC Series Initial support is for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3200 SDK driver peripheral library, installed separately, or built from ext/hal/. Jira: ZEP-1109 Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-10-26 07:49:35 +08:00
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
cc3200: Add support for the TI CC32xx SoC Series Initial support is for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3200 SDK driver peripheral library, installed separately, or built from ext/hal/. Jira: ZEP-1109 Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-10-26 07:49:35 +08:00
*/
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with the NWP interrupt number of 171 caused a hard fault during a subsequent svc #0 instruction during _Swap(). GNU compiler is generating a bit extension instruction (sxtb) which converts a positive IRQ value argument to a negative value when casting to the CMSIS IRQn_Type enum parameter type. This generates a negative index, which then writes to an SCB control register instead of NVIC register, causing a hard fault later on. This issue only occurs when passing interrupt numbers > 0x80 (eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis. The solution here is simply to redefine IRQn_Type to be an unsigned 32 bit integer, while redefining the CMSIS IRQn_Type enum definitions for interrupts less than zero. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-06-03 08:16:43 +08:00
soc: ti_simplelink: add macro to prevent double inclusion of soc.h soc.h needs to use a macro to guard against it being included multiple times. Fixes #17557 Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2019-07-17 06:59:35 +08:00
#ifndef TI_SIMPLELINK_CC32XX_SOC_H_
#define TI_SIMPLELINK_CC32XX_SOC_H_
cc3200: Add support for the TI CC32xx SoC Series Initial support is for the CC3200 SoC, comprising a network coprocessor and Cortex-M4 MPU. This leverages the CC3200 SDK driver peripheral library, installed separately, or built from ext/hal/. Jira: ZEP-1109 Change-Id: I508afc8596c165b309a4ec641c39abadc779eea3 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2016-10-26 07:49:35 +08:00
#include <inc/hw_types.h>
#include <driverlib/prcm.h>
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with the NWP interrupt number of 171 caused a hard fault during a subsequent svc #0 instruction during _Swap(). GNU compiler is generating a bit extension instruction (sxtb) which converts a positive IRQ value argument to a negative value when casting to the CMSIS IRQn_Type enum parameter type. This generates a negative index, which then writes to an SCB control register instead of NVIC register, causing a hard fault later on. This issue only occurs when passing interrupt numbers > 0x80 (eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis. The solution here is simply to redefine IRQn_Type to be an unsigned 32 bit integer, while redefining the CMSIS IRQn_Type enum definitions for interrupts less than zero. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-06-03 08:16:43 +08:00
/*
* CMSIS IRQn_Type enum is broken relative to ARM GNU compiler.
*
* So redefine the IRQn_Type enum to a unsigned int to avoid
* the ARM compiler from sign extending IRQn_Type values higher than 0x80
* into negative IRQ values, which causes hard-to-debug Hard Faults.
*/
typedef u32_t IRQn_Type;
/* Need to keep the remaining from cmsis.h, as Zephyr expects these. */
soc: ti_simplelink: cc32xx: soc.h: Incorrect enum definition. Instead of creating an typedef enum it was creating an object. Signed-off-by: Adithya Baglody <adithya.nagaraj.baglody@intel.com>
2018-11-27 17:30:47 +08:00
typedef enum {
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with the NWP interrupt number of 171 caused a hard fault during a subsequent svc #0 instruction during _Swap(). GNU compiler is generating a bit extension instruction (sxtb) which converts a positive IRQ value argument to a negative value when casting to the CMSIS IRQn_Type enum parameter type. This generates a negative index, which then writes to an SCB control register instead of NVIC register, causing a hard fault later on. This issue only occurs when passing interrupt numbers > 0x80 (eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis. The solution here is simply to redefine IRQn_Type to be an unsigned 32 bit integer, while redefining the CMSIS IRQn_Type enum definitions for interrupts less than zero. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-06-03 08:16:43 +08:00
Reset_IRQn = -15,
NonMaskableInt_IRQn = -14,
HardFault_IRQn = -13,
MemoryManagement_IRQn = -12,
BusFault_IRQn = -11,
UsageFault_IRQn = -10,
SVCall_IRQn = -5,
DebugMonitor_IRQn = -4,
PendSV_IRQn = -2,
SysTick_IRQn = -1,
} CMSIS_IRQn_Type;
#define __CM4_REV 0
#define __MPU_PRESENT 0 /* Zephyr has no MPU support */
dts_fixups: Use DT_ prefix in all defined labels not related to Kconfig These changes were obtained by running a script created by Ulf Magnusson <Ulf.Magnusson@nordicsemi.no> for the following specification: 1. Read the contents of all dts_fixup.h files in Zephyr 2. Check the left-hand side of the #define macros (i.e. the X in #define X Y) 3. Check if that name is also the name of a Kconfig option 3.a If it is, then do nothing 3.b If it is not, then replace CONFIG_ with DT_ or add DT_ if it has neither of these two prefixes 4. Replace the use of the changed #define in the code itself (.c, .h, .ld) Additionally, some tweaks had to be added to this script to catch some of the macros used in the code in a parameterized form, e.g.: - CONFIG_GPIO_STM32_GPIO##__SUFFIX##_BASE_ADDRESS - CONFIG_UART_##idx##_TX_PIN - I2C_SBCON_##_num##_BASE_ADDR and to prevent adding DT_ prefix to the following symbols: - FLASH_START - FLASH_SIZE - SRAM_START - SRAM_SIZE - _ROM_ADDR - _ROM_SIZE - _RAM_ADDR - _RAM_SIZE which are surprisingly also defined in some dts_fixup.h files. Finally, some manual corrections had to be done as well: - name##_IRQ -> DT_##name##_IRQ in uart_stm32.c Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2018-11-13 22:15:23 +08:00
#define __NVIC_PRIO_BITS DT_NUM_IRQ_PRIO_BITS
cc32xx: Redefine CMSIS IRQn_Type enum to unsigned int Previously, calling NVIC_SetPriority(IRQn_Type irqn, ....) with the NWP interrupt number of 171 caused a hard fault during a subsequent svc #0 instruction during _Swap(). GNU compiler is generating a bit extension instruction (sxtb) which converts a positive IRQ value argument to a negative value when casting to the CMSIS IRQn_Type enum parameter type. This generates a negative index, which then writes to an SCB control register instead of NVIC register, causing a hard fault later on. This issue only occurs when passing interrupt numbers > 0x80 (eg: 171 (0xab) for the NWP) to the CMSIS NVIC apis. The solution here is simply to redefine IRQn_Type to be an unsigned 32 bit integer, while redefining the CMSIS IRQn_Type enum definitions for interrupts less than zero. Jira: ZEP-1958 Signed-off-by: Gil Pitney <gil.pitney@linaro.org>
2017-06-03 08:16:43 +08:00
#define __Vendor_SysTickConfig 0 /* Default to standard SysTick */
soc: ti_simplelink: add macro to prevent double inclusion of soc.h soc.h needs to use a macro to guard against it being included multiple times. Fixes #17557 Signed-off-by: Vincent Wan <vincent.wan@linaro.org>
2019-07-17 06:59:35 +08:00
#endif /* TI_SIMPLELINK_CC32XX_SOC_H_ */