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zephyr/soc/arm/microchip_mec/mec1701/dts_fixup.h

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license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
/* SPDX-License-Identifier: Apache-2.0 */
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
/* This file is a temporary workaround for mapping of the generated information
* to the current driver definitions. This will be removed when the drivers
* are modified to handle the generated information, or the mapping of
* generated data matches the driver definitions.
*/
#define DT_NUM_IRQ_PRIO_BITS DT_ARM_V7M_NVIC_E000E100_ARM_NUM_IRQ_PRIORITY_BITS
dts/arm/microchip: Mark uart & i2c nodes as disabled by default Have the SoC dtsi files for microchip mark the devices (uart & i2c) as disabled by default and let the board dts files enable which one's they need/use (which is what's happening already). Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-17 23:45:25 +08:00
#if defined(DT_NS16550_400F2400_REG_SHIFT)
#define DT_NS16550_REG_SHIFT DT_NS16550_400F2400_REG_SHIFT
#elif defined(DT_NS16550_400F2800_REG_SHIFT)
#define DT_NS16550_REG_SHIFT DT_NS16550_400F2800_REG_SHIFT
#endif
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
#define DT_UART_NS16550_PORT_0_BASE_ADDR DT_NS16550_400F2400_BASE_ADDRESS
#define DT_UART_NS16550_PORT_0_CLK_FREQ 1843200
uart/ns16550: Use DT_ prefix for remaining device configs Previous rename from CONFIG_* to DT_* left a few remaining CONFIG_*. So rename them manually now. Fix #13753 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-26 06:26:03 +08:00
#define DT_UART_NS16550_PORT_0_NAME DT_NS16550_400F2400_LABEL
#define DT_UART_NS16550_PORT_0_BAUD_RATE DT_NS16550_400F2400_CURRENT_SPEED
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
#define DT_UART_NS16550_PORT_0_IRQ DT_NS16550_400F2400_IRQ_0
mec1701: fix dts build error This file wasn't migrated to the new DTS define for the IRQ priority. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-25 04:37:46 +08:00
#define DT_UART_NS16550_PORT_0_IRQ_PRI DT_NS16550_400F2400_IRQ_0_PRIORITY
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
#define DT_UART_NS16550_PORT_0_IRQ_FLAGS 0 /* Deault */
#define DT_UART_NS16550_PORT_1_BASE_ADDR DT_NS16550_400F2800_BASE_ADDRESS
#define DT_UART_NS16550_PORT_1_CLK_FREQ 1843200
uart/ns16550: Use DT_ prefix for remaining device configs Previous rename from CONFIG_* to DT_* left a few remaining CONFIG_*. So rename them manually now. Fix #13753 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2019-02-26 06:26:03 +08:00
#define DT_UART_NS16550_PORT_1_NAME DT_NS16550_400F2800_LABEL
#define DT_UART_NS16550_PORT_1_BAUD_RATE DT_NS16550_400F2800_CURRENT_SPEED
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
#define DT_UART_NS16550_PORT_1_IRQ DT_NS16550_400F2800_IRQ_0
mec1701: fix dts build error This file wasn't migrated to the new DTS define for the IRQ priority. Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2019-07-25 04:37:46 +08:00
#define DT_UART_NS16550_PORT_1_IRQ_PRI DT_NS16550_400F2800_IRQ_0_PRIORITY
arch: arm: Add Microchip MEC1701 SoC Initial support for Microchip MEC1701 series is incorporated to the tree. Additional support for UART is also included. This SOC supports two operation modes for interrupts (Direct and Aggregated). For this commit, the interrupts are configured in direct mode. Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@intel.com>
2019-02-07 06:16:55 +08:00
#define DT_UART_NS16550_PORT_1_IRQ_FLAGS 0 /* Default */