2022-11-30 17:33:35 +08:00
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/*
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* Copyright (c) 2022 BrainCo Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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2024-01-09 16:50:44 +08:00
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#include <gd/gd32l23x/gd32l23x.dtsi>
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2022-11-30 17:33:35 +08:00
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/ {
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soc {
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sram1: memory@20004000 {
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compatible = "mmio-sram";
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reg = <0x20004000 DT_SIZE_K(16)>;
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};
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/* Combine SRAM0(16K) and SRAM1(16K), since its address is continuous. */
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sram: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(32)>;
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};
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uart4: usart@40005000 {
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compatible = "gd,gd32-usart";
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reg = <0x40005000 0x400>;
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interrupts = <30 0>;
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clocks = <&cctl GD32_CLOCK_UART4>;
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resets = <&rctl GD32_RESET_UART4>;
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status = "disabled";
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};
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};
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};
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&flash0 {
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reg = <0x08000000 DT_SIZE_K(256)>;
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/* GD32L23X DataSheet not defined the maximum page erase time
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* for flash memory.
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* From other GD32 DataSheets, we can find 1KB page normally have a
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* 300ms max time.
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* Assume GD32L23X use the worst implementation, set the max erase
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* time to 4 times of 1KB page.
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*/
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max-erase-time-ms = <1200>;
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page-size = <DT_SIZE_K(4)>;
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};
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