2021-11-26 17:21:31 +08:00
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/*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Copyright (c) 2021 ASPEED Technology Inc.
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*/
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#ifndef ZEPHYR_SOC_ARM_ASPEED_UTIL_H_
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#define ZEPHYR_SOC_ARM_ASPEED_UTIL_H_
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2022-05-06 17:11:04 +08:00
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#include <zephyr/sys/util.h>
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#include <zephyr/devicetree.h>
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2023-09-14 17:47:58 +08:00
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#include <zephyr/toolchain.h>
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2021-11-26 17:21:31 +08:00
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/* gcc.h doesn't define __section but checkpatch.pl will complain for this. so
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* temporarily add a macro here.
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*/
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#ifndef __section
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#define __section(x) __attribute__((__section__(x)))
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#endif
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/* to make checkpatch.pl happy */
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#define ALIGNED16_SECTION(name) (aligned(16), section(name))
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#define __section_aligned16(name) __attribute__(ALIGNED16_SECTION(name))
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/* non-cached (DMA) memory */
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#if (CONFIG_SRAM_NC_SIZE > 0)
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#define NON_CACHED_BSS __section(".nocache.bss")
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#define NON_CACHED_BSS_ALIGN16 __section_aligned16(".nocache.bss")
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#else
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#define NON_CACHED_BSS
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#define NON_CACHED_BSS_ALIGN16 __aligned(16)
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#endif
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#define reg_read_poll_timeout(map, reg, val, cond, sleep_ms, timeout_ms) \
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({ \
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uint32_t __timeout_tick = Z_TIMEOUT_MS(timeout_ms).ticks; \
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uint32_t __start = sys_clock_tick_get_32(); \
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int __ret = 0; \
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for (;;) { \
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val.value = map->reg.value; \
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if (cond) { \
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break; \
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} \
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if ((sys_clock_tick_get_32() - __start) > __timeout_tick) { \
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__ret = -ETIMEDOUT; \
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break; \
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} \
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if (sleep_ms) { \
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k_msleep(sleep_ms); \
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} \
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} \
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__ret; \
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})
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/* Common reset control device name for all ASPEED SOC family */
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#define ASPEED_RST_CTRL_NAME DT_INST_RESETS_LABEL(0)
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#define DEBUG_HALT() { volatile int halt = 1; while (halt) { __asm__ volatile("nop"); } }
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#endif
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