37 lines
730 B
C
37 lines
730 B
C
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/*
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* Copyright (c) 2016 Cadence Design Systems, Inc.
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* Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
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#define ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_
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#ifndef _ASMLANGUAGE
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#include <kernel_structs.h>
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#define RSR(sr) \
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({u32_t v; \
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__asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
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v; })
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#define WSR(sr, v) \
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do { \
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__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
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} while (false)
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static ALWAYS_INLINE _cpu_t *z_arch_curr_cpu(void)
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{
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_cpu_t *cpu;
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cpu = (_cpu_t *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
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return cpu;
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}
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#endif /* !_ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_XTENSA_ARCH_INLINES_H_ */
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