2019-04-06 21:08:09 +08:00
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/* SPDX-License-Identifier: Apache-2.0 */
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2018-07-31 16:35:20 +08:00
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/* Board level DTS fixup file */
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2018-11-13 22:15:23 +08:00
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#define DT_ETH_E1000_BASE_ADDRESS DT_INTEL_E1000_FEBC0000_BASE_ADDRESS
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#define DT_ETH_E1000_IRQ DT_INTEL_E1000_FEBC0000_IRQ_0
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#define DT_ETH_E1000_IRQ_PRIORITY DT_INTEL_E1000_FEBC0000_IRQ_0_PRIORITY
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#define DT_ETH_E1000_IRQ_FLAGS DT_INTEL_E1000_FEBC0000_IRQ_0_SENSE
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2018-07-31 16:35:20 +08:00
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2019-04-26 14:43:18 +08:00
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#define DT_FLASH_DEV_NAME DT_ZEPHYR_SIM_FLASH_SIM_FLASH_LABEL
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2019-04-18 20:55:30 +08:00
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2019-07-04 20:01:09 +08:00
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#define DT_FLASH_SIM_BASE_ADDRESS DT_SOC_NV_FLASH_0_BASE_ADDRESS
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#define DT_FLASH_SIM_ERASE_BLOCK_SIZE DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE
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#define DT_FLASH_SIM_SIZE DT_SOC_NV_FLASH_0_SIZE
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#define DT_FLASH_SIM_WRITE_BLOCK_SIZE DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE
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2019-09-04 06:48:31 +08:00
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#define DT_FLASH_ERASE_BLOCK_SIZE DT_SOC_NV_FLASH_0_ERASE_BLOCK_SIZE
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#define DT_FLASH_WRITE_BLOCK_SIZE DT_SOC_NV_FLASH_0_WRITE_BLOCK_SIZE
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2018-07-31 16:35:20 +08:00
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/* End of Board Level DTS fixup file */
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