OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/boards/riscv/hifive1/support/hifive1.resc

29 lines
510 B
Plaintext
Raw Normal View History

boards: riscv: hifive1: add support for QEMU and Renode simulation This commit adds required config files for Renode simulation and adds missing QEMU_binary_suffix. It also adds flash and newlib tags to ignore_tags, as flash chip is currently not provided by default in Renode for FE310 and newlib does not fit into the available memory. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-09-13 17:27:04 +08:00
:description: This script is prepared to run Zephyr on SiFive-FE310 board.
:name: SiFive-FE310
$name?="SiFive-FE310"
soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC This commit introduces changes in three places in order to fix the problem with timer-related tests on FE310-based boards: * tests/kernel/sleep/kernel.common.timing * tests/kernel/tickless/tickless_concept/kernel.tickless.concept * tests/kernel/workq/work_queue/kernel.workqueue The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC value back to 32768 Hz to match FE310's datasheet description. The second change is CLINT frequency reduction in Renode simulation model to 16 MHz to correspond with the oscillator frequency given by the FE310's datasheet and the HiFive1 board schematic. This fixes the first two tests. The last change is reducing the MIN_DELAY define to 100. This causes the RISC-V machine timer driver to update the mtimecmp register more often, which in turn addresses the `work_queue/kernel.workqueue` problem with work items finishing prematurely, causing the above-mentioned test to fail. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-05-10 14:25:44 +08:00
set platform
"""
using "platforms/cpus/sifive-fe310.repl"
clint:
frequency: 16000000
"""
boards: riscv: hifive1: add support for QEMU and Renode simulation This commit adds required config files for Renode simulation and adds missing QEMU_binary_suffix. It also adds flash and newlib tags to ignore_tags, as flash chip is currently not provided by default in Renode for FE310 and newlib does not fit into the available memory. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-09-13 17:27:04 +08:00
using sysbus
mach create $name
soc/riscv/sifive-freedom/fe310: use correct SYS_CLOCK_HW_CYCLES_PER_SEC This commit introduces changes in three places in order to fix the problem with timer-related tests on FE310-based boards: * tests/kernel/sleep/kernel.common.timing * tests/kernel/tickless/tickless_concept/kernel.tickless.concept * tests/kernel/workq/work_queue/kernel.workqueue The first change is the modification of the SYS_CLOCK_HW_CYCLES_PER_SEC value back to 32768 Hz to match FE310's datasheet description. The second change is CLINT frequency reduction in Renode simulation model to 16 MHz to correspond with the oscillator frequency given by the FE310's datasheet and the HiFive1 board schematic. This fixes the first two tests. The last change is reducing the MIN_DELAY define to 100. This causes the RISC-V machine timer driver to update the mtimecmp register more often, which in turn addresses the `work_queue/kernel.workqueue` problem with work items finishing prematurely, causing the above-mentioned test to fail. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2022-05-10 14:25:44 +08:00
machine LoadPlatformDescriptionFromString $platform
boards: riscv: hifive1: add support for QEMU and Renode simulation This commit adds required config files for Renode simulation and adds missing QEMU_binary_suffix. It also adds flash and newlib tags to ignore_tags, as flash chip is currently not provided by default in Renode for FE310 and newlib does not fit into the available memory. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2021-09-13 17:27:04 +08:00
sysbus Tag <0x10008000 4> "PRCI_HFROSCCFG" 0xFFFFFFFF
sysbus Tag <0x10008008 4> "PRCI_PLLCFG" 0xFFFFFFFF
cpu PerformanceInMips 320
showAnalyzer uart0
macro reset
"""
sysbus LoadELF $bin
"""
runMacro $reset