2018-05-27 12:49:15 +08:00
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/*
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* Copyright (c) 2018, Intel Corporation
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* All rights reserved.
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*
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* Author: Seppo Ingalsuo <seppo.ingalsuo@linux.intel.com>
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* Liam Girdwood <liam.r.girdwood@linux.intel.com>
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* Keyon Jie <yang.jie@linux.intel.com>
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* Sathish Kuttan <sathish.k.kuttan@intel.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INTEL_DMIC_H__
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#define __INTEL_DMIC_H__
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#include <device.h>
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#define DMIC_HW_IOCLK 38400000
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/* Parameters used in modes computation */
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#define DMIC_HW_BITS_CIC 26
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#define DMIC_HW_BITS_FIR_COEF 20
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#define DMIC_HW_BITS_FIR_GAIN 20
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#define DMIC_HW_BITS_FIR_INPUT 22
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#define DMIC_HW_BITS_FIR_OUTPUT 24
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#define DMIC_HW_BITS_FIR_INTERNAL 26
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#define DMIC_HW_BITS_GAIN_OUTPUT 22
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#define DMIC_HW_FIR_LENGTH_MAX 250
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#define DMIC_HW_CIC_SHIFT_MIN -8
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#define DMIC_HW_CIC_SHIFT_MAX 4
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#define DMIC_HW_FIR_SHIFT_MIN 0
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#define DMIC_HW_FIR_SHIFT_MAX 8
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#define DMIC_HW_CIC_DECIM_MIN 5
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#define DMIC_HW_CIC_DECIM_MAX 31 /* Note: Limited by BITS_CIC */
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#define DMIC_HW_FIR_DECIM_MIN 2
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#define DMIC_HW_FIR_DECIM_MAX 20 /* Note: Practical upper limit */
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#define DMIC_HW_SENS_Q28 BIT(28) /* 1.0 in Q1.28 format */
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#define DMIC_HW_PDM_CLK_MIN 100000 /* Note: Practical min value */
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#define DMIC_HW_DUTY_MIN 20 /* Note: Practical min value */
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#define DMIC_HW_DUTY_MAX 80 /* Note: Practical max value */
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/* DMIC register offsets */
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#define PDM_REG_BASE(pdm) (((pdm) + 1) << 12)
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#define PDM_COEFF_A(pdm) (PDM_REG_BASE(pdm) + 0x400)
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#define PDM_COEFF_B(pdm) (PDM_REG_BASE(pdm) + 0x800)
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/* Global registers */
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#define OUTCONTROL0 0x0000
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#define OUTSTAT0 0x0004
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#define OUTDATA0 0x0008
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#define OUTCONTROL1 0x0100
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#define OUTSTAT1 0x0104
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#define OUTDATA1 0x0108
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/* Local registers in each PDMx */
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#define CIC_CONTROL(pdm) (PDM_REG_BASE(pdm) + 0x000)
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#define CIC_CONFIG(pdm) (PDM_REG_BASE(pdm) + 0x004)
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#define MIC_CONTROL(pdm) (PDM_REG_BASE(pdm) + 0x00c)
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#define FIR_CONTROL_A(pdm) (PDM_REG_BASE(pdm) + 0x020)
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#define FIR_CONFIG_A(pdm) (PDM_REG_BASE(pdm) + 0x024)
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#define DC_OFFSET_LEFT_A(pdm) (PDM_REG_BASE(pdm) + 0x028)
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#define DC_OFFSET_RIGHT_A(pdm) (PDM_REG_BASE(pdm) + 0x02c)
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#define OUT_GAIN_LEFT_A(pdm) (PDM_REG_BASE(pdm) + 0x030)
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#define OUT_GAIN_RIGHT_A(pdm) (PDM_REG_BASE(pdm) + 0x034)
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#define FIR_CONTROL_B(pdm) (PDM_REG_BASE(pdm) + 0x040)
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#define FIR_CONFIG_B(pdm) (PDM_REG_BASE(pdm) + 0x044)
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#define DC_OFFSET_LEFT_B(pdm) (PDM_REG_BASE(pdm) + 0x048)
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#define DC_OFFSET_RIGHT_B(pdm) (PDM_REG_BASE(pdm) + 0x04c)
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#define OUT_GAIN_LEFT_B(pdm) (PDM_REG_BASE(pdm) + 0x050)
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#define OUT_GAIN_RIGHT_B(pdm) (PDM_REG_BASE(pdm) + 0x054)
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/* Register bits */
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/* OUTCONTROL0 bits */
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#define OUTCONTROL0_TIE_BIT BIT(27)
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#define OUTCONTROL0_SIP_BIT BIT(26)
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#define OUTCONTROL0_FINIT_BIT BIT(25)
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#define OUTCONTROL0_FCI_BIT BIT(24)
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#define OUTCONTROL0_TIE(x) SET_BIT(27, x)
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#define OUTCONTROL0_SIP(x) SET_BIT(26, x)
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#define OUTCONTROL0_FINIT(x) SET_BIT(25, x)
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#define OUTCONTROL0_FCI(x) SET_BIT(24, x)
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#define OUTCONTROL0_BFTH(x) SET_BITS(23, 20, x)
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#define OUTCONTROL0_OF(x) SET_BITS(19, 18, x)
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#define OUTCONTROL0_NUMBER_OF_DECIMATORS(x) SET_BITS(17, 15, x)
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#define OUTCONTROL0_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
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#define OUTCONTROL0_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
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#define OUTCONTROL0_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
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#define OUTCONTROL0_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
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#define OUTCONTROL0_TH(x) SET_BITS(5, 0, x)
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/* OUTCONTROL1 bits */
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#define OUTCONTROL1_TIE_BIT BIT(27)
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#define OUTCONTROL1_SIP_BIT BIT(26)
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#define OUTCONTROL1_FINIT_BIT BIT(25)
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#define OUTCONTROL1_FCI_BIT BIT(24)
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#define OUTCONTROL1_TIE(x) SET_BIT(27, x)
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#define OUTCONTROL1_SIP(x) SET_BIT(26, x)
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#define OUTCONTROL1_FINIT(x) SET_BIT(25, x)
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#define OUTCONTROL1_FCI(x) SET_BIT(24, x)
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#define OUTCONTROL1_BFTH(x) SET_BITS(23, 20, x)
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#define OUTCONTROL1_OF(x) SET_BITS(19, 18, x)
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#define OUTCONTROL1_NUMBER_OF_DECIMATORS(x) SET_BITS(17, 15, x)
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#define OUTCONTROL1_IPM_SOURCE_1(x) SET_BITS(14, 13, x)
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#define OUTCONTROL1_IPM_SOURCE_2(x) SET_BITS(12, 11, x)
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#define OUTCONTROL1_IPM_SOURCE_3(x) SET_BITS(10, 9, x)
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#define OUTCONTROL1_IPM_SOURCE_4(x) SET_BITS(8, 7, x)
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#define OUTCONTROL1_TH(x) SET_BITS(5, 0, x)
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/* OUTSTAT0 bits */
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#define OUTSTAT0_AFE_BIT BIT(31)
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#define OUTSTAT0_ASNE_BIT BIT(29)
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#define OUTSTAT0_RFS_BIT BIT(28)
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#define OUTSTAT0_ROR_BIT BIT(27)
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#define OUTSTAT0_FL_MASK MASK(6, 0)
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/* OUTSTAT1 bits */
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#define OUTSTAT1_AFE_BIT BIT(31)
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#define OUTSTAT1_ASNE_BIT BIT(29)
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#define OUTSTAT1_RFS_BIT BIT(28)
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#define OUTSTAT1_ROR_BIT BIT(27)
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#define OUTSTAT1_FL_MASK MASK(6, 0)
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/* CIC_CONTROL bits */
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#define CIC_CONTROL_SOFT_RESET_BIT BIT(16)
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#define CIC_CONTROL_CIC_START_B_BIT BIT(15)
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#define CIC_CONTROL_CIC_START_A_BIT BIT(14)
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#define CIC_CONTROL_MIC_B_POLARITY_BIT BIT(3)
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#define CIC_CONTROL_MIC_A_POLARITY_BIT BIT(2)
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#define CIC_CONTROL_MIC_MUTE_BIT BIT(1)
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#define CIC_CONTROL_STEREO_MODE_BIT BIT(0)
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#define CIC_CONTROL_SOFT_RESET(x) SET_BIT(16, x)
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#define CIC_CONTROL_CIC_START_B(x) SET_BIT(15, x)
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#define CIC_CONTROL_CIC_START_A(x) SET_BIT(14, x)
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#define CIC_CONTROL_MIC_B_POLARITY(x) SET_BIT(3, x)
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#define CIC_CONTROL_MIC_A_POLARITY(x) SET_BIT(2, x)
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#define CIC_CONTROL_MIC_MUTE(x) SET_BIT(1, x)
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#define CIC_CONTROL_STEREO_MODE(x) SET_BIT(0, x)
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/* CIC_CONFIG bits */
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#define CIC_CONFIG_CIC_SHIFT(x) SET_BITS(27, 24, x)
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#define CIC_CONFIG_COMB_COUNT(x) SET_BITS(15, 8, x)
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/* MIC_CONTROL bits */
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#define MIC_CONTROL_PDM_EN_B_BIT BIT(1)
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#define MIC_CONTROL_PDM_EN_A_BIT BIT(0)
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#define MIC_CONTROL_PDM_CLKDIV(x) SET_BITS(15, 8, x)
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#define MIC_CONTROL_PDM_SKEW(x) SET_BITS(7, 4, x)
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#define MIC_CONTROL_CLK_EDGE(x) SET_BIT(3, x)
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#define MIC_CONTROL_PDM_EN_B(x) SET_BIT(1, x)
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#define MIC_CONTROL_PDM_EN_A(x) SET_BIT(0, x)
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/* FIR_CONTROL_A bits */
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#define FIR_CONTROL_A_START_BIT BIT(7)
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#define FIR_CONTROL_A_ARRAY_START_EN_BIT BIT(6)
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#define FIR_CONTROL_A_MUTE_BIT BIT(1)
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#define FIR_CONTROL_A_START(x) SET_BIT(7, x)
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#define FIR_CONTROL_A_ARRAY_START_EN(x) SET_BIT(6, x)
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#define FIR_CONTROL_A_DCCOMP(x) SET_BIT(4, x)
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#define FIR_CONTROL_A_MUTE(x) SET_BIT(1, x)
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#define FIR_CONTROL_A_STEREO(x) SET_BIT(0, x)
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/* FIR_CONFIG_A bits */
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#define FIR_CONFIG_A_FIR_DECIMATION(x) SET_BITS(20, 16, x)
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#define FIR_CONFIG_A_FIR_SHIFT(x) SET_BITS(11, 8, x)
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#define FIR_CONFIG_A_FIR_LENGTH(x) SET_BITS(7, 0, x)
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/* DC offset compensation time constants */
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#define DCCOMP_TC0 0
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#define DCCOMP_TC1 1
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#define DCCOMP_TC2 2
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#define DCCOMP_TC3 3
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#define DCCOMP_TC4 4
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#define DCCOMP_TC5 5
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#define DCCOMP_TC6 6
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#define DCCOMP_TC7 7
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/* DC_OFFSET_LEFT_A bits */
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#define DC_OFFSET_LEFT_A_DC_OFFS(x) SET_BITS(21, 0, x)
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/* DC_OFFSET_RIGHT_A bits */
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#define DC_OFFSET_RIGHT_A_DC_OFFS(x) SET_BITS(21, 0, x)
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/* OUT_GAIN_LEFT_A bits */
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#define OUT_GAIN_LEFT_A_GAIN(x) SET_BITS(19, 0, x)
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/* OUT_GAIN_RIGHT_A bits */
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#define OUT_GAIN_RIGHT_A_GAIN(x) SET_BITS(19, 0, x)
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/* FIR_CONTROL_B bits */
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#define FIR_CONTROL_B_START_BIT BIT(7)
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#define FIR_CONTROL_B_ARRAY_START_EN_BIT BIT(6)
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#define FIR_CONTROL_B_MUTE_BIT BIT(1)
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#define FIR_CONTROL_B_START(x) SET_BIT(7, x)
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#define FIR_CONTROL_B_ARRAY_START_EN(x) SET_BIT(6, x)
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#define FIR_CONTROL_B_DCCOMP(x) SET_BIT(4, x)
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#define FIR_CONTROL_B_MUTE(x) SET_BIT(1, x)
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#define FIR_CONTROL_B_STEREO(x) SET_BIT(0, x)
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/* FIR_CONFIG_B bits */
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#define FIR_CONFIG_B_FIR_DECIMATION(x) SET_BITS(20, 16, x)
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#define FIR_CONFIG_B_FIR_SHIFT(x) SET_BITS(11, 8, x)
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#define FIR_CONFIG_B_FIR_LENGTH(x) SET_BITS(7, 0, x)
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/* DC_OFFSET_LEFT_B bits */
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#define DC_OFFSET_LEFT_B_DC_OFFS(x) SET_BITS(21, 0, x)
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/* DC_OFFSET_RIGHT_B bits */
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#define DC_OFFSET_RIGHT_B_DC_OFFS(x) SET_BITS(21, 0, x)
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/* OUT_GAIN_LEFT_B bits */
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#define OUT_GAIN_LEFT_B_GAIN(x) SET_BITS(19, 0, x)
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/* OUT_GAIN_RIGHT_B bits */
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#define OUT_GAIN_RIGHT_B_GAIN(x) SET_BITS(19, 0, x)
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/* FIR coefficients */
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#define FIR_COEF_A(x) SET_BITS(19, 0, x)
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#define FIR_COEF_B(x) SET_BITS(19, 0, x)
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/* max number of streams supported by hardware 2 = Stream A & B */
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#define DMIC_MAX_STREAMS 2
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#define DMA_HANDSHAKE_DMIC_RXA 0
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#define DMA_HANDSHAKE_DMIC_RXB 1
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2020-05-28 00:26:57 +08:00
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int dmic_configure_dma(struct pcm_stream_cfg *config, uint8_t num_streams);
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int dmic_reload_dma(uint32_t channel, void *buffer, size_t size);
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int dmic_start_dma(uint32_t channel);
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int dmic_stop_dma(uint32_t channel);
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2018-05-27 12:49:15 +08:00
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#endif /* __INTEL_DMIC_H__ */
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