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zephyr/boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig

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intel_s1000: add intel_s1000_crb board intel_s1000_crb board makes use of the intel_s1000 SoC. It has a built-in ROM which gets executed upon applying power. It then executes the secondary bootloader followed by the FW (like zephyr). Change-Id: If334c359b4372a56997c3b2e1eb9250e80847f07 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-06-23 13:57:25 +08:00
CONFIG_MAIN_STACK_SIZE=2048
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=400000000
CONFIG_XTENSA=y
CONFIG_SOC_INTEL_S1000=y
CONFIG_BOARD_INTEL_S1000_CRB=y
CONFIG_SW_ISR_TABLE=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_XTENSA_RESET_VECTOR=y
CONFIG_XTENSA_USE_CORE_CRT1=y
intel_s1000: uart: configure UART for intel_s1000 intel_s1000 uses DesignWare IP for UART. National Semiconductor 16550 (UART) component specification is followed in this IP. Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-30 17:15:44 +08:00
xtensa: intel_s1000: implement interrupt mechanism intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-12 21:02:23 +08:00
CONFIG_MULTI_LEVEL_INTERRUPTS=y
CONFIG_2ND_LEVEL_INTERRUPTS=y
CONFIG_3RD_LEVEL_INTERRUPTS=y
CONFIG_CAVS_ICTL=y
CONFIG_DW_ICTL=y
tests: boards: intel_s1000_crb: select application based on config Add support to enable test application selectively based on defconfig Change-Id: I8111750ff099edd95ffa22c6e312999c801678ea Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-17 02:21:15 +08:00
CONFIG_USB=y
CONFIG_USB_DEVICE_STACK=y
boards: intel_s1000_crb: Assign Intel VID and PID for S1000 CRB Added following configs + CONFIG_USB_DEVICE_VID + CONFIG_USB_DEVICE_PID + CONFIG_USB_DEVICE_MANUFACTURER + CONFIG_USB_DEVICE_PRODUCT to boards/xtensa/intel_s1000_crb/intel_s1000_crb_defconfig Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
2018-05-03 06:38:40 +08:00
CONFIG_USB_DEVICE_VID=0x8087
CONFIG_USB_DEVICE_PID=0x0B1A
CONFIG_USB_DEVICE_MANUFACTURER="Intel(R) Corporation"
CONFIG_USB_DEVICE_PRODUCT="Sue Creek (S1000) ASIC"
tests: boards: intel_s1000_crb: select application based on config Add support to enable test application selectively based on defconfig Change-Id: I8111750ff099edd95ffa22c6e312999c801678ea Signed-off-by: Savinay Dharmappa <savinay.dharmappa@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2018-03-17 02:21:15 +08:00
CONFIG_USB_DEVICE_HID=y
intel_s1000: uart: configure UART for intel_s1000 intel_s1000 uses DesignWare IP for UART. National Semiconductor 16550 (UART) component specification is followed in this IP. Change-Id: Ied7df1dc178d55b6dbe71d729d6383ba07274ea4 Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-08-30 17:15:44 +08:00
CONFIG_CONSOLE=y
CONFIG_SERIAL_HAS_DRIVER=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_UART_NS16550=y