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zephyr/soc/arm/nxp_imx/rt/Kconfig.soc

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
# Kconfig - i.MX RT series
#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#
choice
prompt "i.MX RT Selection"
depends on SOC_SERIES_IMX_RT
config SOC_MIMXRT1051
bool "SOC_MIMXRT1051"
select HAS_MCUX
select HAS_MCUX_CCM
select HAS_MCUX_IGPIO
soc: arm: Enable the lpspi driver and clock for the imxrt soc Enables the mcux lpspi shim driver and subsystem clock for the imxrt soc. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-15 05:18:41 +08:00
select HAS_MCUX_LPSPI
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
select HAS_MCUX_LPUART
select CPU_HAS_FPU
arch: arm: Introduce CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options, which indicate which flavour of MPU is supported by given SoC family. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-08-09 20:47:27 +08:00
select CPU_HAS_ARM_MPU
nxp_imx: Move i.MX RT PLL selects to Kconfig.soc PLL configuration options for i.MX RT SoCs were added in commit 3fd25c64c779ee06e43bfc7c8fb304cbe01d8e5d, but the selects were incorrectly added to the SoC defconfig rather than Kconfig.soc. This resulted in the PLL options not being configured and the part not booting properly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-05 05:22:29 +08:00
select INIT_ARM_PLL
select INIT_SYS_PLL
select INIT_USB1_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
config SOC_MIMXRT1052
bool "SOC_MIMXRT1052"
select HAS_MCUX
select HAS_MCUX_CCM
select HAS_MCUX_IGPIO
soc: arm: Enable the lpspi driver and clock for the imxrt soc Enables the mcux lpspi shim driver and subsystem clock for the imxrt soc. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-15 05:18:41 +08:00
select HAS_MCUX_LPSPI
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
select HAS_MCUX_LPUART
select CPU_HAS_FPU
arch: arm: Introduce CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options This commit introduces CPU_HAS_ARM_MPU and CPU_HAS_NXP_MPU options, which indicate which flavour of MPU is supported by given SoC family. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2018-08-09 20:47:27 +08:00
select CPU_HAS_ARM_MPU
nxp_imx: Move i.MX RT PLL selects to Kconfig.soc PLL configuration options for i.MX RT SoCs were added in commit 3fd25c64c779ee06e43bfc7c8fb304cbe01d8e5d, but the selects were incorrectly added to the SoC defconfig rather than Kconfig.soc. This resulted in the PLL options not being configured and the part not booting properly. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-05 05:22:29 +08:00
select INIT_ARM_PLL
select INIT_SYS_PLL
select INIT_USB1_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
endchoice
if SOC_SERIES_IMX_RT
config SOC_PART_NUMBER_MIMXRT1051CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1051DVL6A
bool
config SOC_PART_NUMBER_MIMXRT1052CVL5A
bool
config SOC_PART_NUMBER_MIMXRT1052DVL6A
bool
config SOC_PART_NUMBER_IMX_RT
string
default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A
default "MIMXRT1052DVL6A" if SOC_PART_NUMBER_MIMXRT1052DVL6A
help
This string holds the full part number of the SoC. It is a hidden option
that you should not set directly. The part number selection choice defines
the default value for this string.
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
config INIT_ARM_PLL
bool "Initialize ARM PLL"
config INIT_SYS_PLL
bool "Initialize SYS PLL"
config INIT_USB1_PLL
bool "Initialize USB1 PLL"
config ARM_DIV
int "ARM clock divider"
range 0 7
config AHB_DIV
int "AHB clock divider"
range 0 7
config IPG_DIV
int "IPG clock divider"
range 0 3
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-12 03:42:40 +08:00
endif # SOC_SERIES_IMX_RT