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zephyr/soc/arm/atmel_sam0/samr21/soc.h

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soc: atmel: add SAMR21 Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233 radio connected internally via SPI. The AT86RF233 is not yet supprted by Zephyr at this point. This code is very much copy & paste from atmel_sam0/samd21 Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2019-02-20 06:14:54 +08:00
/*
* Copyright (c) 2017 Google LLC.
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_ATMEL_SAMR21_SOC_H_
#define ZEPHYR_ATMEL_SAMR21_SOC_H_
#ifndef _ASMLANGUAGE
#define DONT_USE_CMSIS_INIT
#include <zephyr/types.h>
#if defined(CONFIG_SOC_PART_NUMBER_SAMR21E16A)
#include <samr21e16a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E17A)
#include <samr21e17a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E18A)
#include <samr21e18a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21E19A)
#include <samr21e19a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G16A)
#include <samr21g16a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G17A)
#include <samr21g17a.h>
#elif defined(CONFIG_SOC_PART_NUMBER_SAMR21G18A)
#include <samr21g18a.h>
#else
#error Library does not support the specified device.
#endif
#endif /* _ASMLANGUAGE */
/** Processor Clock (HCLK) Frequency */
soc: samr21: Get CPU clock frequency from DTS The SoC initialization code used system clock frequency as a CPU clock frequency. This commit corrects that by obtaining the needed value from DTS. Signed-off-by: Piotr Zięcik <piotr.ziecik@nordicsemi.no>
2019-05-29 20:11:24 +08:00
#define SOC_ATMEL_SAM0_HCLK_FREQ_HZ DT_ARM_CORTEX_M0PLUS_0_CLOCK_FREQUENCY
soc: atmel: add SAMR21 Adds Atmel SAMR21 soc which is based on SAMD21, but with a AT86RF233 radio connected internally via SPI. The AT86RF233 is not yet supprted by Zephyr at this point. This code is very much copy & paste from atmel_sam0/samd21 Signed-off-by: Benjamin Valentin <benpicco@googlemail.com>
2019-02-20 06:14:54 +08:00
/** Master Clock (MCK) Frequency */
#define SOC_ATMEL_SAM0_MCK_FREQ_HZ SOC_ATMEL_SAM0_HCLK_FREQ_HZ
#define SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ 32768
#define SOC_ATMEL_SAM0_OSC8M_FREQ_HZ 8000000
#define SOC_ATMEL_SAM0_GCLK0_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
#if defined(CONFIG_SOC_ATMEL_SAMD_XOSC32K_AS_MAIN)
#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_XOSC32K_FREQ_HZ
#elif defined(CONFIG_SOC_ATMEL_SAMD_OSC8M_AS_MAIN)
#define SOC_ATMEL_SAM0_GCLK1_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
#else
#error Unsupported GCLK1 clock source.
#endif
#define SOC_ATMEL_SAM0_GCLK3_FREQ_HZ SOC_ATMEL_SAM0_OSC8M_FREQ_HZ
#define SOC_ATMEL_SAM0_APBA_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
#define SOC_ATMEL_SAM0_APBB_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
#define SOC_ATMEL_SAM0_APBC_FREQ_HZ SOC_ATMEL_SAM0_MCK_FREQ_HZ
#endif /* ZEPHYR_ATMEL_SAMR21_SOC_H_ */