zephyr/drivers/clock_control/Kconfig.gd32

# Copyright (c) 2022 Teslabs Engineering S.L.
# SPDX-License-Identifier: Apache-2.0

config CLOCK_CONTROL_GD32
	bool "GD32 clock control"
	default y
	depends on DT_HAS_GD_GD32_CCTL_ENABLED
	help
	  Enable driver for Gigadevice Reset Clock Unit (RCU).
drivers: clock_control: gd32: initial support This patch adds a clock control driver for GD32 platforms. It is important to note that the driver is only able to handle peripheral clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On some similar platforms (STM32) this task is embedded in the same clock driver, performed at init time but with no options to do any manipulation at runtime via the API calls. The clock control API as-is is really orthogonal to "system clocks", and it is arguably a bad idea to embed system clock init code in a clock control driver. It can be done at SoC level still using Devicetree as a source of hardware description/initial configuration. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> 2022-09-04 01:06:27 +08:00			`# Copyright (c) 2022 Teslabs Engineering S.L.`
			`# SPDX-License-Identifier: Apache-2.0`

			`config CLOCK_CONTROL_GD32`
			`bool "GD32 clock control"`
			`default y`
			`depends on DT_HAS_GD_GD32_CCTL_ENABLED`
			`help`
			`Enable driver for Gigadevice Reset Clock Unit (RCU).`