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zephyr/drivers/spi/spi_dw_regs.h

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spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
/* spi_dw_regs.h - Designware SPI driver private definitions */
/*
* Copyright (c) 2015 Intel Corporation.
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
*/
#ifndef __SPI_DW_REGS_H__
#define __SPI_DW_REGS_H__
drivers/spi: Adapt DW driver to new SPI API Introducing as well a generic driver helper for CS gpio control and buffer management. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-05-04 16:03:13 +08:00
#ifdef __cplusplus
extern "C" {
#endif
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
#define DW_SPI_REG_CTRLR0 (0x00)
#define DW_SPI_REG_CTRLR1 (0x04)
#define DW_SPI_REG_SSIENR (0x08)
#define DW_SPI_REG_MWCR (0x0c)
#define DW_SPI_REG_SER (0x10)
#define DW_SPI_REG_BAUDR (0x14)
#define DW_SPI_REG_TXFTLR (0x18)
#define DW_SPI_REG_RXFTLR (0x1c)
#define DW_SPI_REG_TXFLR (0x20)
#define DW_SPI_REG_RXFLR (0x24)
#define DW_SPI_REG_SR (0x28)
#define DW_SPI_REG_IMR (0x2c)
#define DW_SPI_REG_ISR (0x30)
#define DW_SPI_REG_RISR (0x34)
#define DW_SPI_REG_TXOICR (0x38)
#define DW_SPI_REG_RXOICR (0x3c)
#define DW_SPI_REG_RXUICR (0x40)
#define DW_SPI_REG_MSTICR (0x44)
#define DW_SPI_REG_ICR (0x48)
#define DW_SPI_REG_DMACR (0x4c)
#define DW_SPI_REG_DMATDLR (0x50)
#define DW_SPI_REG_DMARDLR (0x54)
#define DW_SPI_REG_IDR (0x58)
#define DW_SPI_REG_SSI_COMP_VERSION (0x5c)
#define DW_SPI_REG_DR (0x60)
#define DW_SPI_REG_RX_SAMPLE_DLY (0xf0)
/* Register helpers */
DEFINE_MM_REG_WRITE(ctrlr0, DW_SPI_REG_CTRLR0, 32)
DEFINE_MM_REG_WRITE(ser, DW_SPI_REG_SER, 8)
DEFINE_MM_REG_WRITE(txftlr, DW_SPI_REG_TXFTLR, 32)
DEFINE_MM_REG_WRITE(rxftlr, DW_SPI_REG_RXFTLR, 32)
DEFINE_MM_REG_READ(rxftlr, DW_SPI_REG_RXFTLR, 32)
spi: add macro so that txftlr register can be read Just as rxftlr can be read, a macro is needed so that txftlr can be read. Symmetry. Change-Id: Id987f700d89268feca60850f4fdf512f990f3ab6 Signed-off-by: Chuck Jordan <cjordan@synopsys.com>
2016-05-19 02:10:03 +08:00
DEFINE_MM_REG_READ(txftlr, DW_SPI_REG_TXFTLR, 32)
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
DEFINE_MM_REG_WRITE(dr, DW_SPI_REG_DR, 32)
DEFINE_MM_REG_READ(dr, DW_SPI_REG_DR, 32)
DEFINE_MM_REG_READ(ssi_comp_version, DW_SPI_REG_SSI_COMP_VERSION, 32)
/* ICR is on a unique bit */
DEFINE_TEST_BIT_OP(icr, DW_SPI_REG_ICR, DW_SPI_SR_ICR_BIT)
#define clear_interrupts(addr) test_bit_icr(addr)
#ifdef CONFIG_SPI_DW_CLOCK_GATE
static inline void _clock_config(struct device *dev)
{
struct device *clk;
char *drv = CONFIG_SPI_DW_CLOCK_GATE_DRV_NAME;
clk = device_get_binding(drv);
if (clk) {
struct spi_dw_data *spi = dev->driver_data;
spi->clock = clk;
}
}
static inline void _clock_on(struct device *dev)
{
spi/dw: Make config_info pointers const. Make pointers to struct config_info const in prepration for a const config_info. Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
2016-10-07 02:28:52 +08:00
const struct spi_dw_config *info = dev->config->config_info;
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
struct spi_dw_data *spi = dev->driver_data;
clock_control_on(spi->clock, info->clock_data);
}
static inline void _clock_off(struct device *dev)
{
spi/dw: Make config_info pointers const. Make pointers to struct config_info const in prepration for a const config_info. Change-Id: I28789a7f1f26e4a0d499f5a89a567ae8c61eae51 Signed-off-by: Marcus Shawcroft <marcus.shawcroft@gmail.com>
2016-10-07 02:28:52 +08:00
const struct spi_dw_config *info = dev->config->config_info;
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
struct spi_dw_data *spi = dev->driver_data;
clock_control_off(spi->clock, info->clock_data);
}
#else
#define _clock_config(...)
#define _clock_on(...)
#define _clock_off(...)
#endif /* CONFIG_SPI_DW_CLOCK_GATE */
drivers/spi: Adapt DW driver to new SPI API Introducing as well a generic driver helper for CS gpio control and buffer management. Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2017-05-04 16:03:13 +08:00
#ifdef __cplusplus
}
#endif
spi: dw: Quark SE Sensor Sub-System support Though it's an ARC core, Quark SE SS does not follow the same registers mapping as the official DesignWare document. Some parts are common, some not. Instead of bloating spi_dw.c with a lot of #ifdef or rewriting a whole new driver though the logic is 99% the same, it's then better to: - centralize common macros and definitions into spi_dw.h - have a specific spi_dw_quark_se_ss_reg.h for register map, clock gating and register helpers dedicated to Quark SE SS. - have a spi_dw_regs.h for the common case, i.e. not Quark SE SS. GPIO CS emulation and interrupt masking ends up then in spi_dw.h. Clock gating is specific thus found in respective *_regs.h header. Adding proper interrupt masks to quark_se_ss soc.h file as well. One of the main difference is also the interrupt management: through one line or multiple lines (one for each interrupt: rx, tx and error). On Quark SE Sensor Sub-System it has been set to use multiple lines, thus introducing relevant Kconfig options and managing those when configuring the IRQs. Quark SE SS SPI controller is also working on a lower level, i.e. it requires a tiny bit more logic from the driver. Main example is the data register which needs to be told what is happening from the driver. Taking the opportunity to fix minor logic issues: - ICR register should be cleared by reading, only on error in the ISR handler, but it does not harm doing it anyway and because Quark SE SS requires to clear up interrupt as soon as they have been handled, introducing a clear_interrupts() function called at the and of the ISR handler. - TXFTLR should be set after each spi_transceive() since last pull_data might set it to 0. - Enable the clock (i.e. open the clock gate) at initialization. - No need to mask interrupts at spi_configure() since these are already masked at initialization and at the end of a transaction. - Let's use BIT() macro when relevant. Change-Id: I24344aaf8bff3390383a84436f516951c1a2d2a4 Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2016-01-19 21:43:52 +08:00
#endif /* __SPI_DW_REGS_H__ */