OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/boards/arduino_101/arduino_101_defconfig

17 lines
335 B
Plaintext
Raw Normal View History

kconfig: define architecture as a kconfig variable Do not depend on environment variables and use a kconfig variable for defining the architecture. In addition, remove the X86_32 variable, it just duplicates X86 for not good reason, at least until start supporting MCUs with 64bit. Change-Id: Ia001db81ed007e6a43f34506fed9be1345b88a4b Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-10-09 18:20:52 +08:00
CONFIG_X86=y
Use SoC instead of platform. Change terminology and use SoC instead of platform. An SoC provides features and default configurations available with an SoC. A board implements the SoC and adds more features and IP block specific to the board to extend the SoC functionality such as sensors and debugging features. Change-Id: I15e8d78a6d4ecd5cfb3bc25ced9ba77e5ea1122f Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-17 21:54:35 +08:00
CONFIG_SOC_QUARK_SE=y
kconfig: add board configurations First step for adding the new board layer. Create configurations for the various boards we support on x86 under boards with the new Kconfig variables defining them. The board selection is optional, that means you will be able to run make menuconfig and create your own .config and select any SoC. Change-Id: If08e88e9675d13f0f0501ef6750b9424b15f5dc8 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-12-13 18:54:28 +08:00
CONFIG_BOARD_ARDUINO_101=y
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
CONFIG_CPU_MINUTEIA=y
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
CONFIG_SERIAL=y
serial: simplify interrupt config options Instead of having two config options to specify interrupt triggering conditions, merge them into one option and clarify. This is now similar to other drivers which have interrupt triggers. Change-Id: I4e60c8c45a08d005dcc8256cb89e4c5be7c94307 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2015-12-11 05:29:57 +08:00
CONFIG_UART_IRQ_RISING_EDGE=y
serial/ns16550: refactor (again) to conform to driver model () Renames ns16550.c to uart_ns16550.c. This is to follow the driver naming convention. () Renames functions ns16550_uart_*() to uart_ns16550_*(), following driver naming convention. () UART ports initialization is moved into the driver itself. All the init code in platform config files is removed. () Adds (many) Kconfig options. These don't have to be defined in each platform's board.h anymore. () Renames CONFIG_NS16550_* to CONFIG_UART_NS16550_* () Disable NS16550 for ARC as no port is defined anyway. Change-Id: I76bbe25b9bc75eb62df81e533f84f4f63a5257b7 Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2015-12-02 00:42:19 +08:00
CONFIG_UART_NS16550=y
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
CONFIG_PRINTK=y
ipi: rename to ipm To many people, IPI connotes inter-processor interrupts on SMP systems. Rename this to IPM, or Inter-Processor Mailboxes. Change-Id: I032815e23c69a8297c0a43992132441c240fb71e Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2015-11-13 06:00:47 +08:00
CONFIG_IPM=y
CONFIG_IPM_QUARK_SE=y
CONFIG_IPM_QUARK_SE_MASTER=y
CONFIG_IPM_CONSOLE_RECEIVER=y
x86: add support for the Quark SE platform Intel Quark SE Microcontroller with an onboard sensor subsystem. Processor * Intel Quark SE Processor Core * Intel Pentium® Processor-based x86 ISA compatible CPU * 32MHz clock, 32-bit address bus * 8kB 2-way L1 instruction cache Memory * 384kB of on-die NVM +8kB OTP on-die NVM * 80kB of on-die SRAM Change-Id: I849ec5c1f1639e10a48c9ebab7d3653b88b23eb7 Signed-off-by: Anas Nashif <anas.nashif@intel.com> Signed-off-by: Dirk Brandewie <dirk.j.brandewie@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-11-22 11:25:41 +08:00
CONFIG_ARC_INIT=y
CONFIG_PINMUX=y