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zephyr/boards/arm/olimexino_stm32/olimexino_stm32_defconfig

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boards/olimexino_stm32: add new board Add configuration for OLIMEXINO_STM32 board. By default, the UART console is forwarded to USART1 available on UEXT connector. All GPIO ports available on the connecot headers are enabled. Change-Id: I60b3ff20ea60b5294a3a6c31f4dba0802794f9d8 Origin: Based on nucleo_f103rb board Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-04-13 00:50:14 +08:00
CONFIG_ARM=y
CONFIG_BOARD_OLIMEXINO_STM32=y
CONFIG_SOC_FAMILY_STM32=y
CONFIG_SOC_SERIES_STM32F1X=y
stm32f1: Adapt CONFIG_SOC to STM32Cube values STM32Cube uses SoC defines made to reflect HW heterogeneity that should be taken into account by SW. Aim of this commit is to adapt values used by Zephyr to the same diversity. This will help create new SoC values only when justified by a real hardware difference that should be taken into account by software. For instance, for SoC stm32f103rb following define is used: *STM32F103xB Which means: *Same SW could be used on STM32F103RB and STM32F103VB: same CONFIG_SOC could be used *Different SW should be used on STMF103RB and STM32F103R4: different CONFIG_SOC should be used This change focuses on stm32f1xx series. Change-Id: I5ecfaa52952d04421b27b5e74fb71b4fc108b662 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-03 16:29:04 +08:00
CONFIG_SOC_STM32F103XB=y
boards/olimexino_stm32: add new board Add configuration for OLIMEXINO_STM32 board. By default, the UART console is forwarded to USART1 available on UEXT connector. All GPIO ports available on the connecot headers are enabled. Change-Id: I60b3ff20ea60b5294a3a6c31f4dba0802794f9d8 Origin: Based on nucleo_f103rb board Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-04-13 00:50:14 +08:00
CONFIG_CORTEX_M_SYSTICK=y
# 72MHz system clock
CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=72000000
# enable uart driver
CONFIG_SERIAL=y
CONFIG_UART_STM32=y
# enable USART1
serial: Provide new numbering scheme for stm32 UART There was a misalignment between Zephyr UART device numbering and SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could be confusing for user. This commit allows to align "UART_1" to IP USART_1. Change is propagated to all STM32F103RB/STM32F401RE based boards and respective pinmux drivers Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-14 18:59:45 +08:00
CONFIG_UART_STM32_PORT_1=y
CONFIG_UART_STM32_PORT_1_BAUD_RATE=115200
boards/olimexino_stm32: add new board Add configuration for OLIMEXINO_STM32 board. By default, the UART console is forwarded to USART1 available on UEXT connector. All GPIO ports available on the connecot headers are enabled. Change-Id: I60b3ff20ea60b5294a3a6c31f4dba0802794f9d8 Origin: Based on nucleo_f103rb board Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-04-13 00:50:14 +08:00
# enable console on this port by default
CONFIG_CONSOLE=y
CONFIG_UART_CONSOLE=y
serial: Provide new numbering scheme for stm32 UART There was a misalignment between Zephyr UART device numbering and SoC UART IP. Device "UART_1" was mapped to IP USART_2, which could be confusing for user. This commit allows to align "UART_1" to IP USART_1. Change is propagated to all STM32F103RB/STM32F401RE based boards and respective pinmux drivers Change-Id: Ia8099dfeec7b9c0c686c2a58ccb4dbb1a55b6537 Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
2016-11-14 18:59:45 +08:00
CONFIG_UART_CONSOLE_ON_DEV_NAME="UART_1"
boards/olimexino_stm32: add new board Add configuration for OLIMEXINO_STM32 board. By default, the UART console is forwarded to USART1 available on UEXT connector. All GPIO ports available on the connecot headers are enabled. Change-Id: I60b3ff20ea60b5294a3a6c31f4dba0802794f9d8 Origin: Based on nucleo_f103rb board Signed-off-by: Yannis Damigos <giannis.damigos@gmail.com>
2016-04-13 00:50:14 +08:00
# enable pinmux
CONFIG_PINMUX=y
CONFIG_PINMUX_STM32=y
# enable GPIO ports A, B, C, D
CONFIG_GPIO=y
CONFIG_GPIO_STM32=y
CONFIG_GPIO_STM32_PORTA=y
CONFIG_GPIO_STM32_PORTB=y
CONFIG_GPIO_STM32_PORTC=y
CONFIG_GPIO_STM32_PORTD=y
# clock configuration
CONFIG_CLOCK_CONTROL=y
CONFIG_CLOCK_CONTROL_STM32F10X=y
CONFIG_CLOCK_STM32F10X_SYSCLK_SRC_PLL=y
# use HSE as PLL input
CONFIG_CLOCK_STM32F10X_PLL_SRC_HSE=y
CONFIG_CLOCK_STM32F10X_PLL_MULTIPLIER=9
CONFIG_CLOCK_STM32F10X_AHB_PRESCALER=0
# APB1 clock must not exceed 36MHz limit
CONFIG_CLOCK_STM32F10X_APB1_PRESCALER=2
CONFIG_CLOCK_STM32F10X_APB2_PRESCALER=0