2015-04-11 07:44:37 +08:00
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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2017-01-19 09:01:01 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 07:44:37 +08:00
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*/
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2015-12-04 23:09:39 +08:00
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/**
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* @file
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2016-10-06 06:43:36 +08:00
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* @brief ARM CORTEX-M exception/interrupt exit API
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2015-12-04 23:09:39 +08:00
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*
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*
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* Provides functions for performing kernel handling when exiting exceptions or
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* interrupts that are installed directly in the vector table (i.e. that are not
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* wrapped around by _isr_wrapper()).
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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2016-11-08 23:36:50 +08:00
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#include <kernel_structs.h>
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#include <offsets_short.h>
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2015-04-11 07:44:37 +08:00
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#include <toolchain.h>
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2015-05-29 01:56:47 +08:00
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#include <arch/cpu.h>
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2015-04-11 07:44:37 +08:00
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_ASM_FILE_PROLOGUE
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GTEXT(_ExcExit)
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GTEXT(_IntExit)
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2016-11-08 23:36:50 +08:00
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GDATA(_kernel)
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2016-09-03 04:20:19 +08:00
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2015-07-02 05:22:39 +08:00
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/**
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*
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2015-07-02 05:51:40 +08:00
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* @brief Kernel housekeeping when exiting interrupt handler installed
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2015-07-02 05:22:39 +08:00
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* directly in vector table
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*
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* Kernel allows installing interrupt handlers (ISRs) directly into the vector
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* table to get the lowest interrupt latency possible. This allows the ISR to be
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* invoked directly without going through a software interrupt table. However,
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* upon exiting the ISR, some kernel work must still be performed, namely
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* possible context switching. While ISRs connected in the software interrupt
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* table do this automatically via a wrapper, ISRs connected directly in the
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* vector table must invoke _IntExit() as the *very last* action before
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* returning.
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*
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* e.g.
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*
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* void myISR(void)
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* {
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* printk("in %s\n", __FUNCTION__);
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* doStuff();
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* _IntExit();
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* }
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*
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2015-07-02 05:29:04 +08:00
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* @return N/A
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _IntExit)
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/* _IntExit falls through to _ExcExit (they are aliases of each other) */
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2015-07-02 05:22:39 +08:00
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/**
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*
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2015-07-02 05:51:40 +08:00
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* @brief Kernel housekeeping when exiting exception handler installed
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2015-07-02 05:22:39 +08:00
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* directly in vector table
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*
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* See _IntExit().
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*
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2015-07-02 05:29:04 +08:00
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* @return N/A
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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SECTION_SUBSEC_FUNC(TEXT, _HandlerModeExit, _ExcExit)
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2016-12-15 03:34:29 +08:00
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#ifdef CONFIG_PREEMPT_ENABLED
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kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.
However, this caused two problems:
1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.
2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.
To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.
On the ARM FRDM K64F board, this improvement is seen:
Before:
1- Measure time to switch from ISR back to interrupted task
switching time is 215 tcs = 1791 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 315 tcs = 2625 nsec
After:
1- Measure time to switch from ISR back to interrupted task
switching time is 130 tcs = 1083 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 225 tcs = 1875 nsec
These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.
Fixes ZEP-1401.
Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-02 23:37:27 +08:00
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ldr r0, =_kernel
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2015-04-11 07:44:37 +08:00
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kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.
However, this caused two problems:
1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.
2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.
To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.
On the ARM FRDM K64F board, this improvement is seen:
Before:
1- Measure time to switch from ISR back to interrupted task
switching time is 215 tcs = 1791 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 315 tcs = 2625 nsec
After:
1- Measure time to switch from ISR back to interrupted task
switching time is 130 tcs = 1083 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 225 tcs = 1875 nsec
These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.
Fixes ZEP-1401.
Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-02 23:37:27 +08:00
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ldr r1, [r0, #_kernel_offset_to_current]
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2016-12-22 05:00:35 +08:00
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/*
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* Non-preemptible thread ? Do not schedule (see explanation of
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* preempt field in kernel_struct.h).
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*/
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ldrh r2, [r1, #_thread_offset_to_preempt]
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cmp r2, #_PREEMPT_THRESHOLD
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bhi _EXIT_EXC
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2016-09-03 04:20:19 +08:00
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kernel/arch: enhance the "ready thread" cache
The way the ready thread cache was implemented caused it to not always
be "hot", i.e. there could be some misses, which happened when the
cached thread was taken out of the ready queue. When that happened, it
was not replaced immediately, since doing so could mean that the
replacement might not run because the flow could be interrupted and
another thread could take its place. This was the more conservative
approach that insured that moving a thread to the cache would never be
wasted.
However, this caused two problems:
1. The cache could not be refilled until another thread context-switched
in, since there was no thread in the cache to compare priorities
against.
2. Interrupt exit code would always have to call into C to find what
thread to run when the current thread was not coop and did not have the
scheduler locked. Furthermore, it was possible for this code path to
encounter a cold cache and then it had to find out what thread to run
the long way.
To fix this, filling the cache is now more aggressive, i.e. the next
thread to put in the cache is found even in the case the current cached
thread is context-switched out. This ensures the interrupt exit code is
much faster on the slow path. In addition, since finding the next thread
to run is now always "get it from the cache", which is a simple fetch
from memory (_kernel.ready_q.cache), there is no need to call the more
complex C code.
On the ARM FRDM K64F board, this improvement is seen:
Before:
1- Measure time to switch from ISR back to interrupted task
switching time is 215 tcs = 1791 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 315 tcs = 2625 nsec
After:
1- Measure time to switch from ISR back to interrupted task
switching time is 130 tcs = 1083 nsec
2- Measure time from ISR to executing a different task (rescheduled)
switch time is 225 tcs = 1875 nsec
These are the most dramatic improvements, but most of the numbers
generated by the latency_measure test are improved.
Fixes ZEP-1401.
Change-Id: I2eaac147048b1ec71a93bd0a285e743a39533973
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-12-02 23:37:27 +08:00
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ldr r0, [r0, _kernel_offset_to_ready_q_cache]
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cmp r0, r1
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beq _EXIT_EXC
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2016-09-03 04:20:19 +08:00
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2015-04-11 07:44:37 +08:00
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/* context switch required, pend the PendSV exception */
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ldr r1, =_SCS_ICSR
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ldr r2, =_SCS_ICSR_PENDSV
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str r2, [r1]
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_ExcExitWithGdbStub:
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2016-10-06 06:43:36 +08:00
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_EXIT_EXC:
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2016-12-15 03:34:29 +08:00
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#endif /* CONFIG_PREEMPT_ENABLED */
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2016-10-06 06:43:36 +08:00
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2015-04-11 07:44:37 +08:00
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bx lr
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