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zephyr/boards/arc/nsim/support/mdb_hs_smp.args

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board/nsim: Add support of multi-core ARC HS platform in nSIM Now when SMP support for ARC is available we may introduce a simulation platform which might be used for testing & development for SMP setups. One important note is stand-alone nSIM (as well as its "Free" flavour) doesn't support SMP simulation so we have to switch to use of nSIM via proprietary MetaWare debugger [1] and so: 1. We introduce new emulation target "mdb" 2. It's only possible to run that platform for those who have MetaWare tools installed and valid license. Though QEMU port for ARC is in work at the moment and once we open that port and it has SMP support we'll switch to it and everybody will be able to try ARC HS with SMP. [1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-07-25 19:49:59 +08:00
-arcv2hs
-core2
-rgf_num_banks=2
-rgf_banked_regs=32
-rgf_num_wr_ports=2
-Xatomic
-Xll64
-Xunaligned
-Xcode_density
-Xdiv_rem=radix4
-Xswap
-Xbitscan
-Xmpy_option=qmpyh
-Xshift_assist
-Xbarrel_shifter
-Xfpud_div
-Xfpu_mac
-Xtimer0
-Xtimer0_level=1
-Xtimer1
-Xtimer1_level=0
-Xrtc
-action_points=8
-Xstack_check
-interrupts=72
boards: nsim: add missed -firq for nsim_hs_smp nsim_hs_smp has 2 reg banks, so it should have firq Signed-off-by: Wayne Ren <wei.ren@synopsys.com>
2019-10-24 22:55:32 +08:00
-firq
board/nsim: Add support of multi-core ARC HS platform in nSIM Now when SMP support for ARC is available we may introduce a simulation platform which might be used for testing & development for SMP setups. One important note is stand-alone nSIM (as well as its "Free" flavour) doesn't support SMP simulation so we have to switch to use of nSIM via proprietary MetaWare debugger [1] and so: 1. We introduce new emulation target "mdb" 2. It's only possible to run that platform for those who have MetaWare tools installed and valid license. Though QEMU port for ARC is in work at the moment and once we open that port and it has SMP support we'll switch to it and everybody will be able to try ARC HS with SMP. [1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-07-25 19:49:59 +08:00
-interrupt_priorities=2
-ext_interrupts=70
-interrupt_base=0x0
-dcache=65536,64,2,a
-dcache_feature=2
-dcache_uncached_region
-dcache_mem_cycles=2
-icache=65536,64,4,a
-icache_feature=2
-arconnect
-connect_ics=1
-connect_ics_num_semas=16
-connect_icm=1
-connect_icm_sram_size=512
-connect_icm_sram_prot=none
-connect_pmu=1
-connect_idu=2
-connect_idu_cirqnum=64
-connect_gfrc=1
-connect_icd=2
-connect_ici=2
ARC: NSIM: switch to ns16550 UART model Switch nSIM from custom ARC UART to ns16550 model. That will allow us to use zephyr images built for nSIM on other platforms like HAPS, QEMU, etc... This patch do: * switch nSIM board to ns16550 UART usage * change nSIM simulator configuration to use ns16550 UART model * drop checks for CONFIG_UART_NSIM in ARC code * update nSIM documentation Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
2020-07-13 23:41:12 +08:00
-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=0,use_connect=1
board/nsim: Add support of multi-core ARC HS platform in nSIM Now when SMP support for ARC is available we may introduce a simulation platform which might be used for testing & development for SMP setups. One important note is stand-alone nSIM (as well as its "Free" flavour) doesn't support SMP simulation so we have to switch to use of nSIM via proprietary MetaWare debugger [1] and so: 1. We introduce new emulation target "mdb" 2. It's only possible to run that platform for those who have MetaWare tools installed and valid license. Though QEMU port for ARC is in work at the moment and once we open that port and it has SMP support we'll switch to it and everybody will be able to try ARC HS with SMP. [1] https://www.synopsys.com/dw/ipdir.php?ds=sw_metaware Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
2019-07-25 19:49:59 +08:00
-on=nsim_print-sys-arch
-noprofile
-nogoifmain
arc: nsim_hs_smp: use the default value of mdb instrs_per_pass option Instrs_per_pass option specify the number of instructions excuted before simulator switches operations. the default value is 512. If we specify a small value for it the debugger's overhead will increase significantly for simulation because of the time taken to rapidly switch operations. And the overhead will cause some time critical task failure. Restore instrs_per_pass value from 10 to default 512, we will have a good sanitycheck result for nsim_hs_smp. Signed-off-by: Watson Zeng <zhiwei@synopsys.com>
2020-11-23 14:37:20 +08:00
-instrs_per_pass=512