30 lines
1.3 KiB
Plaintext
30 lines
1.3 KiB
Plaintext
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SDMMC Subsystem Test
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##################
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This test is designed to verify the SD subsystem stack implementation,
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and run stress tests to verify large data transfers succeed using the
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subsystem. Due to the differences between underlying SD host controller drivers,
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this test also serves as a complete test for the SDHC driver implementation in
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use. It requires an SD card be connected to the board to pass, and will
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perform destructive I/O on the card, wiping any data present. The test has
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the following phases:
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* Init test: verify the SD host controller can detect card presence, and
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test the initialization flow of the SDMMC subsystem to verify that the stack
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can correctly initialize an SD card.
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* IOCTL test: verify the SD subsystem correctly implements IOCTL calls required
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for block devices in Zephyr.
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* Read test: verify that single block reads work, followed by multiple
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block reads. Ensure the subsystem will reject reads beyond the end of
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the card's stated size.
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* Write test: verify that single block writes work, followed by multiple
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block writes. Ensure the subsystem will reject writes beyond the end of
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the card's stated size.
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* R/W test: write data to the SD card, and verify that it is able
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to be read back without error. Perform this R/W combination at several
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sector locations across the SD card.
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