2015-04-11 07:44:37 +08:00
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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2017-01-19 09:01:01 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 07:44:37 +08:00
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*/
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2015-12-04 23:09:39 +08:00
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/**
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* @file
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* @brief New thread creation for ARM Cortex-M
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*
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2016-12-18 22:42:55 +08:00
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* Core thread related primitives for the ARM Cortex-M processor architecture.
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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2016-12-23 21:35:34 +08:00
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#include <kernel.h>
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2015-04-11 07:44:37 +08:00
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#include <toolchain.h>
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2016-11-08 23:36:50 +08:00
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#include <kernel_structs.h>
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2015-06-15 02:19:10 +08:00
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#include <wait_q.h>
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2015-08-18 04:13:56 +08:00
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#ifdef CONFIG_INIT_STACKS
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#include <string.h>
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#endif /* CONFIG_INIT_STACKS */
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2015-04-11 07:44:37 +08:00
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2015-08-20 23:04:01 +08:00
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#if defined(CONFIG_THREAD_MONITOR)
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2016-10-25 22:30:19 +08:00
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/*
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* Add a thread to the kernel's list of active threads.
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2015-07-02 05:22:39 +08:00
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*/
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2017-03-27 22:35:09 +08:00
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static ALWAYS_INLINE void thread_monitor_init(struct k_thread *thread)
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2015-04-11 07:44:37 +08:00
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{
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unsigned int key;
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key = irq_lock();
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2017-03-27 22:35:09 +08:00
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thread->next_thread = _kernel.threads;
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_kernel.threads = thread;
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2015-04-11 07:44:37 +08:00
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irq_unlock(key);
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}
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2016-10-25 22:30:19 +08:00
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#else
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2017-03-27 22:35:09 +08:00
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#define thread_monitor_init(thread) \
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2016-10-25 22:30:19 +08:00
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do {/* do nothing */ \
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} while ((0))
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2015-08-20 23:04:01 +08:00
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#endif /* CONFIG_THREAD_MONITOR */
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2015-04-11 07:44:37 +08:00
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2015-07-02 05:22:39 +08:00
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/**
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*
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2017-04-20 01:16:15 +08:00
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* @brief Initialize a new thread from its stack space
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2015-07-02 05:22:39 +08:00
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*
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2017-03-27 22:35:09 +08:00
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* The control structure (thread) is put at the lower address of the stack. An
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2015-07-02 05:22:39 +08:00
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* initial context, to be "restored" by __pendsv(), is put at the other end of
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* the stack, and thus reusable by the stack when not needed anymore.
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*
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* The initial context is an exception stack frame (ESF) since exiting the
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* PendSV exception will want to pop an ESF. Interestingly, even if the lsb of
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* an instruction address to jump to must always be set since the CPU always
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* runs in thumb mode, the ESF expects the real address of the instruction,
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* with the lsb *not* set (instructions are always aligned on 16 bit halfwords).
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* Since the compiler automatically sets the lsb of function addresses, we have
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* to unset it manually before storing it in the 'pc' field of the ESF.
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*
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* <options> is currently unused.
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*
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2015-10-21 00:42:33 +08:00
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* @param pStackMem the aligned stack memory
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* @param stackSize stack size in bytes
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* @param pEntry the entry point
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* @param parameter1 entry point to the first param
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* @param parameter2 entry point to the second param
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* @param parameter3 entry point to the third param
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2016-09-03 04:20:19 +08:00
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* @param priority thread priority
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2016-11-04 22:26:27 +08:00
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* @param options thread options: K_ESSENTIAL, K_FP_REGS
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2015-10-21 00:42:33 +08:00
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*
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2015-07-02 05:29:04 +08:00
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* @return N/A
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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2016-11-15 05:46:14 +08:00
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void _new_thread(char *pStackMem, size_t stackSize,
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2016-11-20 01:31:53 +08:00
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_thread_entry_t pEntry,
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2015-10-21 00:42:33 +08:00
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void *parameter1, void *parameter2, void *parameter3,
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int priority, unsigned options)
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2015-04-11 07:44:37 +08:00
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{
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2016-11-09 04:44:05 +08:00
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_ASSERT_VALID_PRIO(priority, pEntry);
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2016-06-17 04:49:07 +08:00
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__ASSERT(!((uint32_t)pStackMem & (STACK_ALIGN - 1)),
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"stack is not aligned properly\n"
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"%d-byte alignment required\n", STACK_ALIGN);
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2015-04-11 07:44:37 +08:00
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char *stackEnd = pStackMem + stackSize;
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struct __esf *pInitCtx;
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2017-03-27 22:35:09 +08:00
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struct k_thread *thread = (struct k_thread *) pStackMem;
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2015-04-11 07:44:37 +08:00
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2015-05-26 02:31:59 +08:00
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#ifdef CONFIG_INIT_STACKS
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2015-08-18 04:13:56 +08:00
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memset(pStackMem, 0xaa, stackSize);
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2015-05-26 02:31:59 +08:00
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#endif
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2015-08-20 23:04:01 +08:00
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/* carve the thread entry struct from the "base" of the stack */
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2015-04-11 07:44:37 +08:00
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pInitCtx = (struct __esf *)(STACK_ROUND_DOWN(stackEnd) -
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sizeof(struct __esf));
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2015-08-20 23:04:01 +08:00
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pInitCtx->pc = ((uint32_t)_thread_entry) & 0xfffffffe;
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2015-04-11 07:44:37 +08:00
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pInitCtx->a1 = (uint32_t)pEntry;
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pInitCtx->a2 = (uint32_t)parameter1;
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pInitCtx->a3 = (uint32_t)parameter2;
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pInitCtx->a4 = (uint32_t)parameter3;
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pInitCtx->xpsr =
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0x01000000UL; /* clear all, thumb bit is 1, even if RO */
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2017-03-27 22:35:09 +08:00
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_init_thread_base(&thread->base, priority, _THREAD_PRESTART, options);
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2016-09-03 04:20:19 +08:00
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/* static threads overwrite it afterwards with real value */
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2017-03-27 22:35:09 +08:00
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thread->init_data = NULL;
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thread->fn_abort = NULL;
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2015-04-11 07:44:37 +08:00
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2015-08-20 23:04:01 +08:00
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#ifdef CONFIG_THREAD_CUSTOM_DATA
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2015-04-11 07:44:37 +08:00
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/* Initialize custom data field (value is opaque to kernel) */
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2017-03-27 22:35:09 +08:00
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thread->custom_data = NULL;
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2015-04-11 07:44:37 +08:00
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#endif
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2016-03-03 07:31:26 +08:00
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#ifdef CONFIG_THREAD_MONITOR
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/*
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2017-03-27 22:35:09 +08:00
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* In debug mode thread->entry give direct access to the thread entry
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2016-03-03 07:31:26 +08:00
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* and the corresponding parameters.
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*/
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2017-03-27 22:35:09 +08:00
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thread->entry = (struct __thread_entry *)(pInitCtx);
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2016-03-03 07:31:26 +08:00
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#endif
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2017-03-27 22:35:09 +08:00
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thread->callee_saved.psp = (uint32_t)pInitCtx;
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thread->arch.basepri = 0;
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2015-04-11 07:44:37 +08:00
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kernel/arm: fix race condition when setting _Swap() return value
There was a possible race condition when setting the return value of a
thread that is pending, from an ISR.
A kernel function causes a thread to pend, with the following series of
steps:
- disable interrupts
- move current thread to wait_q
- call _Swap
Depending if running on M3/4 or M0+, _Swap will either issue a svc #0,
or pend PendSV directly. The same problem exists in both cases.
M3/4:
__svc will:
- enable interrupts
- trigger __pendsv
M0+:
_Swap() will enable interrupts.
__pendsv will:
- save register context including PSP into the thread struct
If an interrupt occurs between interrupts being enabled them and
__pendsv saving PSP, and the ISR sets the pending thread's return value,
this will happen:
- sees the thread in a wait_q
- removes it
- makes it ready
- calls _set_thread_return_value
- _set_thread_return_value looks at the thread's saved PSP to poke
the value
In this scenario, PSP hasn't yet been updated by __pendsv so it's a
stale value from the previous context switch, resulting in unpredictable
word on the stack getting set to the return value.
There is no way to fix this issue and still have the return value being
delivered directly in the pending thread's exception stack frame, in the
M0+ case. There will always be a window between the unlocking of
interrupts and PendSV being handled. On M3/4, it could be possible with
the mix of SVC and PendSV, since the exception stack frame is created in
the __svc handler. However, because we want to keep the two
implementations as close as possible, and there were talks of moving
M3/4 to using PendSV only, to save an exception, the approach taken
solves both cases.
The approach taken is similar to the ARC and Nios2 ports, where
there is a field in the thread structure that holds the return value.
_Swap() then loads r0/a1 with that value just before returning.
Fixes ZEP-1289.
Change-Id: Iee7e06fe3f8ded84aff918fd43408c7f589344d9
Signed-off-by: Benjamin Walsh <benjamin.walsh@windriver.com>
2016-11-16 07:45:43 +08:00
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/* swap_return_value can contain garbage */
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2017-03-27 22:35:09 +08:00
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/*
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* initial values in all other registers/thread entries are
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* irrelevant.
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*/
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2015-04-11 07:44:37 +08:00
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2017-03-27 22:35:09 +08:00
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thread_monitor_init(thread);
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2015-04-11 07:44:37 +08:00
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}
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