OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/boards/riscv/qemu_riscv32/Kconfig.board

14 lines
300 B
Plaintext
Raw Normal View History

license: cleanup: add SPDX Apache-2.0 license identifier Update the files which contain no license information with the 'Apache-2.0' SPDX license identifier. Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of Zephyr, which is Apache version 2. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2019-04-06 21:08:09 +08:00
# SPDX-License-Identifier: Apache-2.0
boards: added support for the qemu_riscv32 board The qemu_riscv32 board makes use of: 1) the uart_riscv_qemu driver 2) the riscv_qemu_timer driver Change-Id: I413e3990a66bc62a0d15d82ebca6940b381fed43 Signed-off-by: Jean-Paul Etienne <fractalclone@gmail.com>
2017-01-11 07:24:31 +08:00
config BOARD_QEMU_RISCV32
bool "QEMU RISCV32 target"
boards: qemu_riscv32 use virt machine Upgrade board specification to use the VirtIO board. Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2020-12-09 02:37:36 +08:00
depends on SOC_RISCV_VIRT
boards: mark qemu targets with a unified Kconfig This will allow checking if we are building for QEMU globally, without having to know the exact architecture and board name. Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-07-26 20:08:21 +08:00
select QEMU_TARGET
tests: fp_sharing: Enable build-only tests for RISC-V QEMU platform Enables build-only tests for the qemu_riscv32 platform. Signed-off-by: Corey Wharton <coreyw7@fb.com>
2020-04-16 09:13:52 +08:00
select CPU_HAS_FPU
board: riscv: add qemu_riscv32_xip board to test XIP mode Add a variant riscv build target that only is run for tests tagged with "xip". Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-03-08 00:42:17 +08:00
config BOARD_QEMU_RISCV32_XIP
bool "QEMU RISCV32 XIP target"
depends on SOC_RISCV_SIFIVE_FREEDOM
select QEMU_TARGET
select CPU_HAS_FPU