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zephyr/soc/openisa/rv32m1/soc_offsets.h

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arch: soc: riscv32: Separate soc offsets from soc context save The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-03 08:46:26 +08:00
/*
* Copyright (c) 2018 Foundries.io Ltd
*
* SPDX-License-Identifier: Apache-2.0
*/
/*
* Extra definitions required for CONFIG_RISCV_SOC_OFFSETS.
*/
#ifndef SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
#define SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_
soc: riscv: openisa_rv32m1: add missing includes <soc.h> is needed to pull some APIs defined in soc.h. <fsl_device_registers.h> is needed to access EVENT0/1 addresses. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-18 22:27:19 +08:00
#include <fsl_device_registers.h>
arch: soc: riscv32: Separate soc offsets from soc context save The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-03 08:46:26 +08:00
#ifdef CONFIG_SOC_OPENISA_RV32M1_RI5CY
soc: riscv: rv32m1: Fix optional context save Saving an extended context for RV32M1 should be optional, but it was broken due to the offset calculation not taking the according option into account. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2020-06-07 20:39:51 +08:00
#ifdef CONFIG_RISCV_SOC_CONTEXT_SAVE
arch: soc: riscv32: Separate soc offsets from soc context save The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-03 08:46:26 +08:00
/*
* Ensure offset macros are available in <offsets.h>.
*
* Also create a macro which contains the value of &EVENT0->INTPTPENDCLEAR,
* for use in assembly.
*/
#define GEN_SOC_OFFSET_SYMS() \
GEN_OFFSET_SYM(soc_esf_t, lpstart0); \
GEN_OFFSET_SYM(soc_esf_t, lpend0); \
GEN_OFFSET_SYM(soc_esf_t, lpcount0); \
GEN_OFFSET_SYM(soc_esf_t, lpstart1); \
GEN_OFFSET_SYM(soc_esf_t, lpend1); \
GEN_OFFSET_SYM(soc_esf_t, lpcount1); \
GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
(uint32_t)&EVENT0->INTPTPENDCLEAR)
soc: riscv: rv32m1: Fix optional context save Saving an extended context for RV32M1 should be optional, but it was broken due to the offset calculation not taking the according option into account. Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2020-06-07 20:39:51 +08:00
#else
#define GEN_SOC_OFFSET_SYMS() \
GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
(uint32_t)&EVENT0->INTPTPENDCLEAR)
#endif /* CONFIG_RISCV_SOC_CONTEXT_SAVE */
arch: soc: riscv32: Separate soc offsets from soc context save The zero-riscy core on the rv32m1 soc does not implement hardware loop extensions and thus should not enable RISCV_SOC_CONTEXT_SAVE, however it does still need access to the EVENTx_INTPTPENDCLEAR symbol which comes from GEN_SOC_OFFSET_SYMS(). Split out the soc offset symbols into a separate config so we can enable them without enabling soc context saving. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-03 08:46:26 +08:00
#endif /* CONFIG_SOC_OPENISA_RV32M1_RI5CY */
#ifdef CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY
#define GEN_SOC_OFFSET_SYMS() \
GEN_ABSOLUTE_SYM(__EVENT_INTPTPENDCLEAR, \
(uint32_t)&EVENT1->INTPTPENDCLEAR)
#endif /* CONFIG_SOC_OPENISA_RV32M1_ZERO_RISCY */
#endif /* SOC_RISCV32_OPENISA_RV32M1_SOC_OFFSETS_H_ */