72 lines
3.0 KiB
C
72 lines
3.0 KiB
C
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/*
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* Copyright (c) 2021-2022 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_FPGA_ZYNQMP_H
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#define ZEPHYR_DRIVERS_FPGA_ZYNQMP_H
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#define PCAP_STATUS (*(volatile uint32_t *) (0xFFCA3010))
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#define PCAP_RESET (*(volatile uint32_t *) (0xFFCA300C))
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#define PCAP_CTRL (*(volatile uint32_t *) (0xFFCA3008))
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#define PCAP_RDWR (*(volatile uint32_t *) (0xFFCA3004))
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#define PMU_REQ_PWRUP_TRIG (*(volatile uint32_t *) (0xFFD80120))
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#define PCAP_PROG (*(volatile uint32_t *) (0xFFCA3000))
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#define CSU_SSS_CFG (*(volatile uint32_t *) (0xFFCA0008))
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#define CSUDMA_SRC_ADDR (*(volatile uint32_t *) (0xFFC80000))
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#define CSUDMA_SRC_SIZE (*(volatile uint32_t *) (0xFFC80004))
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#define CSUDMA_SRC_I_STS (*(volatile uint32_t *) (0xFFC80014))
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#define CSUDMA_SRC_ADDR_MSB (*(volatile uint32_t *) (0xFFC80028))
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#define PWR_STATUS (*(volatile uint32_t *) (0xFFD80110))
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#define PMU_GLOBAL_ISO_STATUS (*(volatile uint32_t *) (0xFFD80310))
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#define PMU_GLOBAL_PWRUP_EN (*(volatile uint32_t *) (0xFFD80118))
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#define PCAP_CLK_CTRL (*(volatile uint32_t *) (0xFF5E00A4))
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#define PMU_GLOBAL_ISO_INT_EN (*(volatile uint32_t *) (0xFFD80318))
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#define PMU_GLOBAL_ISO_TRIG (*(volatile uint32_t *) (0xFFD80320))
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#define IDCODE (*(volatile uint32_t *) (0xFFCA0040))
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#define BITSTREAM ((volatile uint32_t *) (0x01000000))
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#define PWR_PL_MASK 0x800000U
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#define ISO_MASK 0x4U
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#define PCAP_RESET_MASK 0x1U
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#define PCAP_PROG_RESET_MASK 0x0U
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#define PCAP_PR_MASK 0x1U
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#define PCAP_WRITE_MASK 0x0U
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#define PCAP_PL_INIT_MASK 0x4U
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#define PCAP_CLKACT_MASK 0x1000000U
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#define PCAP_PCAP_SSS_MASK 0x5U
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#define PCAP_PL_DONE_MASK 0x8U
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#define PCAP_CFG_RESET 0x40U
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#define CSUDMA_I_STS_DONE_MASK 0x2U
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#define CSUDMA_SRC_ADDR_MASK 0xFFFFFFFCU
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#define CSUDMA_SRC_SIZE_SHIFT 0x2U
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#define IDCODE_MASK 0xFFFFFFF
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#define ZU2_IDCODE 0x4711093
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#define ZU3_IDCODE 0x4710093
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#define ZU4_IDCODE 0x4721093
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#define ZU5_IDCODE 0x4720093
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#define ZU6_IDCODE 0x4739093
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#define ZU7_IDCODE 0x4730093
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#define ZU9_IDCODE 0x4738093
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#define ZU11_IDCODE 0x4740093
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#define ZU15_IDCODE 0x4750093
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#define ZU17_IDCODE 0x4759093
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#define ZU19_IDCODE 0x4758093
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#define ZU21_IDCODE 0x47E1093
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#define ZU25_IDCODE 0x47E5093
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#define ZU27_IDCODE 0x47E4093
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#define ZU28_IDCODE 0x47E0093
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#define ZU29_IDCODE 0x47E2093
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#define ZU39_IDCODE 0x47E6093
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#define ZU43_IDCODE 0x47FD093
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#define ZU46_IDCODE 0x47F8093
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#define ZU47_IDCODE 0x47FF093
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#define ZU48_IDCODE 0x47FB093
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#define ZU49_IDCODE 0x47FE093
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#define XLNX_BITSTREAM_SECTION_LENGTH(data) (*(data + 1) | *data << 0x8U);
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#endif /* ZEPHYR_DRIVERS_FPGA_ZYNQMP_H */
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