zephyr/soc/arm/nxp_imx/rt/CMakeLists.txt

#
# Copyright (c) 2017, NXP
#
# SPDX-License-Identifier: Apache-2.0
#

zephyr_sources(
  soc.c
  )

zephyr_sources_ifdef(CONFIG_ARM_MPU_IMX_RT arm_mpu_regions.c)
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com> 2017-08-12 03:42:40 +08:00			`#`
			`# Copyright (c) 2017, NXP`
			`#`
			`# SPDX-License-Identifier: Apache-2.0`
			`#`

			`zephyr_sources(`
			`soc.c`
			`)`
arm: Enable the ARM MPU on the NXP i.MX RT SoC and board Unlike other NXP SoCs currently in Zephyr, the mimxrt1052 has the ARM MPU rather than the NXP MPU. Start out by enabling it with a simple set of memory regions for "flash" (ITCM), "ram" (DTCM), and the peripheral buses. More regions will need to be added when we implement support for external memories. Tested with: - samples/mpu/mpu_stack_guard_test - tests/kernel/mem_protect/protection Signed-off-by: Maureen Helm <maureen.helm@nxp.com> 2017-11-11 22:54:34 +08:00
			`zephyr_sources_ifdef(CONFIG_ARM_MPU_IMX_RT arm_mpu_regions.c)`