zephyr/dts/bindings/pinctrl/nxp,mcux-rt11xx-pinctrl.yaml

# Copyright (c) 2022 NXP
# SPDX-License-Identifier: Apache-2.0

description: |
  The node has the 'pinctrl' node label set in MCUX RT SoC's devicetree. These
  nodes can be autogenerated using the MCUXpresso config tools combined with
  the rt_dts_gen.py script in NXP's HAL. The mux, mode, input, daisy, and cfg
  fields in a group select the pins to be configured, and the remaining
  devicetree properties set configuration values for those pins
  for example, here is an group configuring LPUART1 pins:

  group0 {
      pinmux = <&iomuxc_gpio_ad_25_lpuart1_rxd>,
          <&iomuxc_gpio_ad_24_lpuart1_txd>;
      drive-strength = "high";
      slew-rate = "slow";
  };

  This will select GPIO_AD_25 as LPUART1 RX, and GPIO_AD_24 as LPUART1 TX.
  Both pins will be configured with a weak latch, high drive strength,
  and slow slew rates.
  Note that the soc level iomuxc dts file can be examined to find the possible
  pinmux options. Here are the affects of each property on the
  IOMUXC SW_PAD_CTL register:
  drive-open-drain: ODE/ODE_LPSR=1
  input-enable: SION=1 (in SW_MUX_CTL_PAD register)
  bias-pull-down: PUE=1, PUS=0
  bias-pull-up: PUE=1, PUS=1
  bias-disable: PULL=11 (in supported registers)
  slew-rate: SRE=<enum_idx>
  drive-strength: DSE=<enum_idx>

  If only required properties are supplied, the pin will have the following
  configuration:
  ODE=0
  SION=0
  PUE=0
  PUS=0
  SRE=0
  DSE=0

  For registers with PDVR and PULL fields, these are the defaults:
  PULL=11
  PDRV=0


compatible: "nxp,mcux-rt11xx-pinctrl"

include: base.yaml

child-binding:
  description: MCUX RT pin controller pin group
  child-binding:
    description: |
      MCUX RT pin controller pin configuration node.

    include:
      - name: pincfg-node.yaml
        property-allowlist:
          - drive-open-drain
          - input-enable
          - bias-disable
          - bias-pull-down
          - bias-pull-up

    properties:
      pinmux:
        required: true
        type: phandles
        description: |
          Pin mux selections for this group. See the soc level iomuxc DTSI file
          for a defined list of these options.
      drive-strength:
        type: string
        enum:
          - "normal"
          - "high"
        description: |
          Pin output drive strength. Sets the DSE field in the IOMUXC peripheral.
          0 (normal) - sets pin to normal drive strength
          1 (high) - sets pin to high drive strength
      slew-rate:
        type: string
        enum:
          - "fast"
          - "slow"
        description: |
          Select slew rate for pin. Corresponds to SRE field in IOMUXC peripheral
          0 (fast) — Fast Slew Rate
          1 (slow) — Slow Slew Rate