57 lines
1.3 KiB
YAML
57 lines
1.3 KiB
YAML
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# Copyright (c) 2024 STMicroelectronics
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32WB0 Reset and Clock controller node for STM32WB0 devices
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This node is in charge of the system clock ('SYSCLK') source
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selection and generation.
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compatible: "st,stm32wb0-rcc"
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include: [clock-controller.yaml, base.yaml]
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properties:
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reg:
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required: true
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"#clock-cells":
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const: 2
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clock-frequency:
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required: true
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type: int
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description: |
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default frequency in Hz for clock output
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slow-clock:
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type: phandle
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description: |
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Slow clock source selection.
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On STM32WB0, all slow clock devices are clocked from the same
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slow clock source, which is selected by this property.
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The slow clock can be either clk_lsi, clk_lse, or clk_16mhz_div512.
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clksys-prescaler:
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type: int
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required: true
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enum:
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- 1
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- 2
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- 4
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- 8
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- 16
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- 32
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- 64
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description: |
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CLK_SYS prescaler. Defines actual core clock frequency (CLK_SYS) based
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on system frequency input (SYSCLK).
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The CLK_SYS is used to clock the CPU, AHB, APB, memories and PKA.
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NOTE: if the 32MHz HSE is used as SYSCLK source, the prescaler cannot
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be set to 64.
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clock-cells:
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- bus
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- bits
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