43 lines
885 B
YAML
43 lines
885 B
YAML
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# Copyright (c) 2023, Linaro ltd
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# SPDX-License-Identifier: Apache-2.0
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description: |
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STM32F4 PLL I2S node binding:
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Takes same input as Main PLL. PLLM factor and PLL source are common with Main PLL
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1 output clocks supported, the frequency can be computed with the following formula:
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f(PLL_R) = f(VCO clock) / PLLR --> PLLI2S
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with f(VCO clock) = f(PLL clock input) × (PLLNI2S / PLLM)
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compatible: "st,stm32f4-plli2s-clock"
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include: [clock-controller.yaml, base.yaml]
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properties:
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"#clock-cells":
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const: 0
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mul-n:
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type: int
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required: true
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description: |
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PLLI2S multiplication factor for VCO
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Valid range may vary between parts: 50 - 432 , 192 - 432
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div-r:
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type: int
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required: true
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description: |
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PLLI2S division factor for I2S Clocks
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enum:
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- 2
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- 3
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- 4
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- 5
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- 6
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- 7
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