zephyr/dts/bindings/clock/renesas,ra-cgc-pclk-block.yaml

# Copyright (c) 2024 Renesas Electronics Corporation
# SPDX-License-Identifier: Apache-2.0

description: Renesas RA Clock Control node pclk block

compatible: "renesas,ra-cgc-pclk-block"

include: [clock-controller.yaml, base.yaml]

properties:
  clocks:
    required: true
soc: renesas: ra: Add initial support for RA8M1 SOC series Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-01-11 11:53:22 +08:00			`# Copyright (c) 2024 Renesas Electronics Corporation`
			`# SPDX-License-Identifier: Apache-2.0`

dts: bindings: clock: Change clock control binding for Renesas RA Background of this modification is to make clock control driver code provided by Renesas vendor to support for Renesas MCU on Zephyr. Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-06-20 17:49:31 +08:00			`description: Renesas RA Clock Control node pclk block`
soc: renesas: ra: Add initial support for RA8M1 SOC series Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-01-11 11:53:22 +08:00
dts: bindings: clock: Change clock control binding for Renesas RA Background of this modification is to make clock control driver code provided by Renesas vendor to support for Renesas MCU on Zephyr. Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-06-20 17:49:31 +08:00			`compatible: "renesas,ra-cgc-pclk-block"`
soc: renesas: ra: Add initial support for RA8M1 SOC series Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-01-11 11:53:22 +08:00
			`include: [clock-controller.yaml, base.yaml]`

			`properties:`
dts: renesas_ra: Referencing clocks change to DeviceTree's standard. DeviceTree typically references the clock source using the `clocks` property defined in `base.yaml`, so we'll change it to this. Also delete the custom clock source definitions in `renesas,ra-cgc-pclk-block.yaml`, `renesas,ra-cgc-pclk.yaml`, and `renesas,ra-cgc-pll.yaml`. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com> 2024-09-12 22:04:31 +08:00			`clocks:`
soc: renesas: ra: Add initial support for RA8M1 SOC series Add minimal support for RA8M1 SOC series. Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com> Signed-off-by: Quy Tran <quy.tran.pz@renesas.com> 2024-01-11 11:53:22 +08:00			`required: true`