zephyr/tests/kernel/interrupt/testcase.yaml

tests:
  arch.interrupt:
    arch_exclude: nios2 riscv32
    platform_exclude: hexiwear_kw40z frdm_kw41z frdm_kl25z nucleo_f103rb
        nucleo_f091rc olimexino_stm32 usb_kw24d512 stm32_min_dev_blue
        stm32_min_dev_black v2m_beetle
    tags: interrupt
tests: add tests to validate interrupt nesting feature This test is intended to verify the interrupt nesting. Interrupt nesting feature allows an ISR to be preempted in mid-execution if a higher priority interrupt is signaled. The lower priority ISR resumes execution once the higher priority ISR has completed its processing. Signed-off-by: Ajay Kishore <ajay.kishore@intel.com> 2018-03-09 21:43:10 +08:00			`tests:`
			`arch.interrupt:`
tests: interrupt: disable riscv32 This is a new test and we have riscv32 failing on that all of the sudden. Disabling while we look into it and identify if that is a testcase issue or not. Signed-off-by: Anas Nashif <anas.nashif@intel.com> 2018-10-17 08:50:08 +08:00			`arch_exclude: nios2 riscv32`
tests: kernel: interrupt: Exclude platforms test isnt valid on The test assumes that the last to IRQ numbers will be free, this isn't a valid assumption and now that we detect multiple ISRs registering for the some IRQ line, we see failures because of this assumption on some platforms. Exclude those platforms from this test for the time being. Signed-off-by: Kumar Gala <kumar.gala@linaro.org> 2019-02-06 22:50:14 +08:00			`platform_exclude: hexiwear_kw40z frdm_kw41z frdm_kl25z nucleo_f103rb`
tests: kernel: Exclude platforms stm32_min_dev_* Exclude the two variants of smt32_min_dev (stm32_min_dev_black and stm32_min_dev_blue) from kernel tests. Signed-off-by: Siddharth Chandrasekaran <siddharth@embedjournal.com> 2019-04-25 00:52:00 +08:00			`nucleo_f091rc olimexino_stm32 usb_kw24d512 stm32_min_dev_blue`
			`stm32_min_dev_black v2m_beetle`
tests: add tests to validate interrupt nesting feature This test is intended to verify the interrupt nesting. Interrupt nesting feature allows an ISR to be preempted in mid-execution if a higher priority interrupt is signaled. The lower priority ISR resumes execution once the higher priority ISR has completed its processing. Signed-off-by: Ajay Kishore <ajay.kishore@intel.com> 2018-03-09 21:43:10 +08:00			`tags: interrupt`