OrgZephyr/zephyr
OrgZephyr
/
zephyr
mirror of https://github.com/zephyrproject-rtos/zephyr.git
1
0
Fork 0
Code Issues Releases Wiki Activity
zephyr/boards/riscv/qemu_riscv64/qemu_riscv64_smp_defconfig

19 lines
385 B
Plaintext
Raw Normal View History

boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp Based on qemu_riscv32 and qemu_riscv64, add minimal SMP support using the "virt" machine. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-01-12 07:38:14 +08:00
# SPDX-License-Identifier: Apache-2.0
CONFIG_SOC_SERIES_RISCV_VIRT=y
CONFIG_SOC_RISCV_VIRT=y
riscv: smp: update the qemu_riscv32/64 configs No usermode nor stackguard CI tests are performed if CONFIG_RISCV_PMP is not set. In turn, this requires a larger privileged stack on RV64 just like the non SMP case. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-09-21 13:05:14 +08:00
CONFIG_BOARD_QEMU_RISCV64_SMP=y
CONFIG_PRIVILEGED_STACK_SIZE=2048
boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp Based on qemu_riscv32 and qemu_riscv64, add minimal SMP support using the "virt" machine. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-01-12 07:38:14 +08:00
CONFIG_CONSOLE=y
CONFIG_SERIAL=y
CONFIG_UART_CONSOLE=y
CONFIG_STACK_SENTINEL=y
CONFIG_XIP=n
CONFIG_SMP=y
boards: Change defconfigs to use CONFIG_MP_MAX_NUM_CPUS Move to using CONFIG_MP_MAX_NUM_CPUS in defconfig as we phase out CONFIG_MP_NUM_CPUS. Signed-off-by: Kumar Gala <kumar.gala@intel.com>
2022-10-19 00:26:41 +08:00
CONFIG_MP_MAX_NUM_CPUS=2
boards/riscv: Add qemu_riscv32_smp and qemu_riscv64_smp Based on qemu_riscv32 and qemu_riscv64, add minimal SMP support using the "virt" machine. Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2022-01-12 07:38:14 +08:00
CONFIG_QEMU_ICOUNT=n
CONFIG_IDLE_STACK_SIZE=1024
riscv: smp: update the qemu_riscv32/64 configs No usermode nor stackguard CI tests are performed if CONFIG_RISCV_PMP is not set. In turn, this requires a larger privileged stack on RV64 just like the non SMP case. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2022-09-21 13:05:14 +08:00
CONFIG_RISCV_PMP=y
kernel: spinlock: Ticket spinlocks Basic spinlock implementation is based on single atomic variable and doesn't guarantee locking fairness across multiple CPUs. It's even possible that single CPU will win the contention every time which will result in a live-lock. Ticket spinlocks provide a FIFO order of lock aquisition which resolves such unfairness issue at the cost of slightly increased memory footprint. Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>
2023-08-08 18:31:18 +08:00
CONFIG_TICKET_SPINLOCKS=y