87 lines
7.0 KiB
ReStructuredText
87 lines
7.0 KiB
ReStructuredText
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Zephyr support status on ARC processors
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#######################################
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Overview
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********
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This page describes current state of Zephyr for ARC processors and some future
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plans. Please note that
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* plans are given without exact deadlines
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* software features require corresponding hardware to be present and
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configured the proper way
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* not all the features can be enabled at the same time
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Support status
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**************
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Legend:
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**Y** - yes, supported; **N** - no, not supported; **WIP** - Work In Progress;
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**TBD** - to be decided
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| | **Processor families** |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| | **EM** | **HS3x/4x** | **EV** | **HS6x** |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Port status | upstreamed | upstreamed | WIP | WIP |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| **Features** |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Closely coupled memories (ICCM, DCCM) [#f1]_ | Y | Y | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Execution with caches - Instruction/Data, L1/L2 caches | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Hardware-assisted unaligned memory access | Y [#f2]_ | Y | TBD | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Regular interrupts with multiple priority levels, direct interrupts | Y | Y | TBD | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Fast interrupts, separate register banks for fast interrupts | Y | Y | TBD | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Hardware floating point unit (FPU) | Y | Y | N | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Symmetric multiprocessing (SMP) support, switch-based | N/A | Y | TBD | WIP |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Hardware-assisted stack checking | Y | Y | TBD | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Hardware-assisted atomic operations | N/A | Y | TBD | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| DSP ISA | Y | N [#f3]_ | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| DSP AGU/XY extensions | N [#f3]_ | N [#f3]_ | TBD | TBD |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Userspace | Y | N | N | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Memory protection unit (MPU) | Y | Y | TBD | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| Memory management unit (MMU) | N/A | N | N/A | N |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| SecureShield | Y | N/A | N/A | N/A |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| **Toolchains** |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| GNU (open source GCC-based) | Y | Y | N | WIP |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| MetaWare (proprietary Clang-based) | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| **Simulators** |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| QEMU (open source) [#f4]_ | Y | Y | N | WIP |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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| nSIM (proprietary, provided by MetaWare Development Tools) | Y | Y | Y | Y |
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+---------------------------------------------------------------------+------------+-------------+--------+----------+
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Notes
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*****
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.. [#f1] usage of CCMs is limited on SMP systems
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.. [#f2] except the systems with secure features (SecureShield) due to HW
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limitation
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.. [#f3] We only support save/restore ACCL/ACCH registers in task's context.
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Rest of DSP/AGU registers save/restore isn't implemented but kernel
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itself does not use these registers. This allows single task per
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core to use DSP/AGU safely.
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.. [#f4] QEMU doesn't support all the ARC processor's HW features. For the
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detailed info please check the ARC QEMU documentation
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