2017-10-12 01:06:20 +08:00
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/*
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* Copyright (c) 2017 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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2019-12-18 16:31:56 +08:00
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#ifndef ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CAVS_H_
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#define ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CAVS_H_
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2017-10-12 01:06:20 +08:00
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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2020-05-01 02:33:38 +08:00
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typedef void (*cavs_ictl_config_irq_t)(const struct device *port);
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2017-10-12 01:06:20 +08:00
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struct cavs_ictl_config {
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2020-05-28 00:26:57 +08:00
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uint32_t irq_num;
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uint32_t isr_table_offset;
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2017-10-12 01:06:20 +08:00
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cavs_ictl_config_irq_t config_func;
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};
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struct cavs_ictl_runtime {
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2020-05-28 00:26:57 +08:00
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uint32_t base_addr;
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2017-10-12 01:06:20 +08:00
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};
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struct cavs_registers {
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2020-05-28 00:26:57 +08:00
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uint32_t disable_il; /* il_msd - offset 0x00 */
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uint32_t enable_il; /* il_mcd - offset 0x04 */
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uint32_t disable_state_il; /* il_md - offset 0x08 */
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uint32_t status_il; /* il_sd - offset 0x0C */
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2017-10-12 01:06:20 +08:00
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};
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#ifdef __cplusplus
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}
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#endif
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2019-12-18 16:31:56 +08:00
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#endif /* ZEPHYR_DRIVERS_INTERRUPT_CONTROLLER_INTC_CAVS_H_ */
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