2018-07-31 17:44:34 +08:00
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/*
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* Copyright (c) 2018 Intel Corporation.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ETH_E1000_PRIV_H
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#define ETH_E1000_PRIV_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CTRL_SLU (1 << 6) /* Set Link Up */
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#define TCTL_EN (1 << 1)
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#define RCTL_EN (1 << 1)
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#define ICR_TXDW (1) /* Transmit Descriptor Written Back */
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#define ICR_TXQE (1 << 1) /* Transmit Queue Empty */
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#define ICR_RXO (1 << 6) /* Receiver Overrun */
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#define IMS_RXO (1 << 6) /* Receiver FIFO Overrun */
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2018-11-12 20:34:23 +08:00
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#define RCTL_MPE (1 << 4) /* Multicast Promiscuous Enabled */
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2018-07-31 17:44:34 +08:00
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#define TDESC_EOP (1) /* End Of Packet */
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#define TDESC_RS (1 << 3) /* Report Status */
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#define RDESC_STA_DD (1) /* Descriptor Done */
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#define TDESC_STA_DD (1) /* Descriptor Done */
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#define ETH_ALEN 6 /* TODO: Add a global reusable definition in OS */
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enum e1000_reg_t {
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CTRL = 0x0000, /* Device Control */
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ICR = 0x00C0, /* Interrupt Cause Read */
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ICS = 0x00C8, /* Interrupt Cause Set */
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IMS = 0x00D0, /* Interrupt Mask Set */
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RCTL = 0x0100, /* Receive Control */
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TCTL = 0x0400, /* Transmit Control */
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RDBAL = 0x2800, /* Rx Descriptor Base Address Low */
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RDBAH = 0x2804, /* Rx Descriptor Base Address High */
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RDLEN = 0x2808, /* Rx Descriptor Length */
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RDH = 0x2810, /* Rx Descriptor Head */
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RDT = 0x2818, /* Rx Descriptor Tail */
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TDBAL = 0x3800, /* Tx Descriptor Base Address Low */
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TDBAH = 0x3804, /* Tx Descriptor Base Address High */
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TDLEN = 0x3808, /* Tx Descriptor Length */
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TDH = 0x3810, /* Tx Descriptor Head */
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TDT = 0x3818, /* Tx Descriptor Tail */
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RAL = 0x5400, /* Receive Address Low */
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RAH = 0x5404, /* Receive Address High */
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};
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/* Legacy TX Descriptor */
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struct e1000_tx {
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2020-05-28 00:26:57 +08:00
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uint64_t addr;
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uint16_t len;
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uint8_t cso;
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uint8_t cmd;
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uint8_t sta;
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uint8_t css;
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uint16_t special;
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2018-07-31 17:44:34 +08:00
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};
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/* Legacy RX Descriptor */
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struct e1000_rx {
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2020-05-28 00:26:57 +08:00
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uint64_t addr;
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uint16_t len;
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uint16_t csum;
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uint8_t sta;
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uint8_t err;
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uint16_t special;
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2018-07-31 17:44:34 +08:00
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};
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struct e1000_dev {
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volatile struct e1000_tx tx __aligned(16);
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volatile struct e1000_rx rx __aligned(16);
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2020-06-27 03:03:17 +08:00
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mm_reg_t address;
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2020-05-11 15:49:55 +08:00
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/* If VLAN is enabled, there can be multiple VLAN interfaces related to
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* this physical device. In that case, this iface pointer value is not
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* really used for anything.
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*/
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2018-07-31 17:44:34 +08:00
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struct net_if *iface;
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2020-05-28 00:26:57 +08:00
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uint8_t mac[ETH_ALEN];
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uint8_t txb[NET_ETH_MTU];
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uint8_t rxb[NET_ETH_MTU];
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2020-05-15 20:29:51 +08:00
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#if defined(CONFIG_ETH_E1000_PTP_CLOCK)
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const struct device *ptp_clock;
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float clk_ratio;
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#endif
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2018-07-31 17:44:34 +08:00
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};
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static const char *e1000_reg_to_string(enum e1000_reg_t r)
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__attribute__((unused));
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#define iow32(_dev, _reg, _val) do { \
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2019-04-19 06:47:36 +08:00
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LOG_DBG("iow32 %s 0x%08x", e1000_reg_to_string(_reg), (_val)); \
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sys_write32(_val, (_dev)->address + (_reg)); \
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2022-07-20 14:37:40 +08:00
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} while (false)
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2018-07-31 17:44:34 +08:00
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#define ior32(_dev, _reg) \
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({ \
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2020-05-28 00:26:57 +08:00
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uint32_t val = sys_read32((_dev)->address + (_reg)); \
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2018-11-12 20:39:34 +08:00
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LOG_DBG("ior32 %s 0x%08x", e1000_reg_to_string(_reg), val); \
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2018-07-31 17:44:34 +08:00
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val; \
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})
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#ifdef __cplusplus
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}
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#endif
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#endif /* ETH_E1000_PRIV_H_ */
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