zephyr/dts/x86/intel_curie.dtsi

#include "skeleton.dtsi"
#include <dt-bindings/interrupt-controller/intel-ioapic.h>

#define __SIZE_K(x) (x * 1024)

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu@0 {
			device_type = "cpu";
			compatible = "intel,quark";
			reg = <0>;
		};

		cpu@1 {
			device_type = "cpu";
			compatible = "arc";
			reg = <1>;
		};

		intc: ioapic@fec00000  {
			compatible = "intel,ioapic";
			reg = <0xfec00000 0x100000>;
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	flash0: flash@40010000 {
		reg = <0x40010000 DT_FLASH_SIZE>;
	};

	flash1: flash@40030000 {
		reg = <0x40030000 DT_FLASH_SIZE>;
	};

	sram0: memory@a8007000 {
		device_type = "memory";
		compatible = "mmio-sram";
		reg = <0xa8007000 DT_SRAM_SIZE>;
	};

	soc {
		#address-cells = <1>;
		#size-cells = <1>;
		compatible = "simple-bus";
		ranges;

		rtc: rtc@b0000400 {
			compatible = "intel,qmsi-rtc";
			reg = <0xb0000400 0x400>;
			interrupts = <11  IRQ_TYPE_EDGE_RISING>;
			interrupt-parent = <&intc>;

			clock-frequency = <32768>;
		};

		uart0: uart@b0002000 {
			compatible = "intel,qmsi-uart";
			reg = <0xb0002000 0x400>;
			label = "UART_0";
			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&intc>;

			status = "disabled";
		};

		uart1: uart@b0002400 {
			compatible = "intel,qmsi-uart";
			reg = <0xb0002400 0x400>;
			label = "UART_1";
			interrupts = <6 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&intc>;


			status = "disabled";
		};

		gpio: gpio@b000c000 {
			compatible = "intel,qmsi-gpio";
			reg = <0xb00c00 0x400>;
			interrupts = <8 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-parent = <&intc>;

			gpio-controller;
			#gpio-cells = <2>;
		};

		usb_cdc: virtualcom@0 {
			compatible = "intel,qmsi-usb";
			label = "CDC_ACM";
		};
	};
};