2015-04-11 07:44:37 +08:00
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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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2017-01-19 09:01:01 +08:00
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* SPDX-License-Identifier: Apache-2.0
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2015-04-11 07:44:37 +08:00
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*/
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2015-12-04 23:09:39 +08:00
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/**
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* @file
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* @brief Stack helpers for Cortex-M CPUs
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*
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2015-10-21 00:42:33 +08:00
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* Stack helper functions.
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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#ifndef _ARM_CORTEXM_STACK__H_
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#define _ARM_CORTEXM_STACK__H_
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2016-11-08 23:36:50 +08:00
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#include <kernel_structs.h>
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2015-04-28 01:40:11 +08:00
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#include <asm_inline.h>
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2015-04-11 07:44:37 +08:00
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2016-01-23 01:38:49 +08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2015-04-11 07:44:37 +08:00
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#ifdef CONFIG_STACK_ALIGN_DOUBLE_WORD
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#define STACK_ALIGN_SIZE 8
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#else
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#define STACK_ALIGN_SIZE 4
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#endif
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#ifdef _ASMLANGUAGE
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/* nothing */
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#else
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2015-04-27 23:28:19 +08:00
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extern char _interrupt_stack[CONFIG_ISR_STACK_SIZE];
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2015-04-11 07:44:37 +08:00
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2015-07-02 05:22:39 +08:00
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/**
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*
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2015-07-02 05:51:40 +08:00
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* @brief Setup interrupt stack
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2015-07-02 05:22:39 +08:00
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*
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* On Cortex-M, the interrupt stack is registered in the MSP (main stack
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* pointer) register, and switched to automatically when taking an exception.
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*
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2015-07-02 05:29:04 +08:00
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* @return N/A
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2015-07-02 05:22:39 +08:00
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*/
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2015-04-11 07:44:37 +08:00
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static ALWAYS_INLINE void _InterruptStackSetup(void)
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{
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2016-07-21 03:42:10 +08:00
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uint32_t msp = (uint32_t)(_interrupt_stack + CONFIG_ISR_STACK_SIZE);
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2015-04-15 06:15:52 +08:00
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2015-04-11 07:44:37 +08:00
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_MspSet(msp);
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}
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#endif /* _ASMLANGUAGE */
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2016-01-23 01:38:49 +08:00
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#ifdef __cplusplus
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}
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#endif
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2015-04-11 07:44:37 +08:00
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#endif /* _ARM_CORTEXM_STACK__H_ */
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