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zephyr/include/arch/cpu.h

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First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
/* cpu.h - automatically selects the correct arch.h file to include */
/*
* Copyright (c) 1997-2014 Wind River Systems, Inc.
*
license: Replace Apache boilerplate with SPDX tag Replace the existing Apache 2.0 boilerplate header with an SPDX tag throughout the zephyr code tree. This patch was generated via a script run over the master branch. Also updated doc/porting/application.rst that had a dependency on line numbers in a literal include. Manually updated subsys/logging/sys_log.c that had a malformed header in the original file. Also cleanup several cases that already had a SPDX tag and we either got a duplicate or missed updating. Jira: ZEP-1457 Change-Id: I6131a1d4ee0e58f5b938300c2d2fc77d2e69572c Signed-off-by: David B. Kinder <david.b.kinder@intel.com> Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2017-01-19 09:01:01 +08:00
* SPDX-License-Identifier: Apache-2.0
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
*/
headers: Fix headers across the project Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-15 01:43:44 +08:00
#ifndef ZEPHYR_INCLUDE_ARCH_CPU_H_
#define ZEPHYR_INCLUDE_ARCH_CPU_H_
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
kernel: activate arch interface headers Duplicate definitions elsewhere have been removed. A couple functions which are defined by the arch interface to be non-inline, but were implemented inline by native_posix and intel64, have been moved to non-inline. Some missing conditional compilation for z_arch_irq_offload() has been fixed, as this is an optional feature. Some massaging of native_posix headers to get everything in the right scope. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-10-04 06:20:41 +08:00
#include <sys/arch_inlines.h>
arch/x86: refactor arch.h Some of the elements of arch.h can be shared between subarches, so put them in a common file and factor out the rest. Placeholder left for the Intel64 definitions to be added later. Signed-off-by: Charles E. Youse <charles.youse@intel.com>
2019-07-05 02:27:20 +08:00
#if defined(CONFIG_X86)
#include <arch/x86/arch.h>
Rename VXMICRO_ARCH_arm -> CONFIG_ARM Change-Id: I32b2e39781825504e7936b3df0c864988650c35c Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-06 10:27:08 +08:00
#elif defined(CONFIG_ARM)
Renaming include/nanokernel to include/arch Renaming the directory include/nanokernel to be include/arch, which better reflects the real nature of the directory and the contents inside. Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2015-05-29 01:56:47 +08:00
#include <arch/arm/arch.h>
Rename VXMICRO_ARCH_arc -> CONFIG_ARC Change-Id: I4aca181523f50f43ee01e1be0c20a9ad844ef618 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-06 10:27:49 +08:00
#elif defined(CONFIG_ARC)
Renaming include/nanokernel to include/arch Renaming the directory include/nanokernel to be include/arch, which better reflects the real nature of the directory and the contents inside. Change-Id: I2bc33ebc6715e2f0403227a558279fdf52398ade Signed-off-by: Dan Kalowsky <daniel.kalowsky@intel.com>
2015-05-29 01:56:47 +08:00
#include <arch/arc/arch.h>
nios2: basic build, non-functional Basic build framework for Nios2. Everything is stubbed out, we just want to have a build going so that we can start to parallelize implementation tasks. This patch is not intended to be functional, but should be able to produce a binary for all the nanokernel-based sanity checks. Change-Id: I12dd8ca4a2273f7662bee46175822c9bbd99202a Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2016-04-22 05:47:09 +08:00
#elif defined(CONFIG_NIOS2)
#include <arch/nios2/arch.h>
riscv32: rename to riscv With the upcoming riscv64 support, it is best to use "riscv" as the subdirectory name and common symbols as riscv32 and riscv64 support code is almost identical. Then later decide whether 32-bit or 64-bit compilation is wanted. Redirects for the web documentation are also included. Then zephyrbot complained about this: " New files added that are not covered in CODEOWNERS: dts/riscv/microsemi-miv.dtsi dts/riscv/riscv32-fe310.dtsi Please add one or more entries in the CODEOWNERS file to cover those files " So I assigned them to those who created them. Feel free to readjust as necessary. Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2019-07-18 01:17:05 +08:00
#elif defined(CONFIG_RISCV)
#include <arch/riscv/arch.h>
Xtensa port: Added support in arch/cpu.h for Xtensa cores. Change-Id: If4a053f6164fd2fa30f148e6e907f662cda50722 Signed-off-by: Mazen NEIFER <mazen@nestwave.com>
2017-01-21 03:52:29 +08:00
#elif defined(CONFIG_XTENSA)
#include <arch/xtensa/arch.h>
arch: native: Run Zephyr natively in a POSIX OS A new arch (posix) which relies on pthreads to emulate the context switching A new soc for it (inf_clock) which emulates a CPU running at an infinely high clock (so when the CPU is awaken it runs till completion in 0 time) A new board, which provides a trivial system tick timer and irq generation. Origin: Original Fixes #1891 Signed-off-by: Alberto Escolar Piedras <alpi@oticon.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2017-10-03 22:31:55 +08:00
#elif defined(CONFIG_ARCH_POSIX)
#include <arch/posix/arch.h>
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#else
Rename VXMICRO_ARCH and VXMICRO Change-Id: I6f3858de98333ec466aa876c5f2887faa8e276e2 Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2015-06-06 10:33:49 +08:00
#error "Unknown Architecture"
First commit Signed-off-by: <inaky.perez-gonzalez@intel.com>
2015-04-11 07:44:37 +08:00
#endif
headers: Fix headers across the project Any word started with underscore followed by and uppercase letter or a second underscore is a reserved word according with C99. Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2018-09-15 01:43:44 +08:00
#endif /* ZEPHYR_INCLUDE_ARCH_CPU_H_ */