53 lines
1.4 KiB
C
53 lines
1.4 KiB
C
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/*
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* Copyright (c) 2023 Nordic Semiconductor ASA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc32xx_pinctrl
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#include <zephyr/arch/cpu.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/ti-cc32xx-pinctrl.h>
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#define MEM_GPIO_PAD_CONFIG_MSK 0xFFFU
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/* pin to pad mapping (255 indicates invalid pin) */
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static const uint8_t pin2pad[] = {
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10U, 11U, 12U, 13U, 14U, 15U, 16U, 17U, 255U, 255U, 18U, 19U, 20U,
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21U, 22U, 23U, 24U, 40U, 28U, 29U, 25U, 255U, 255U, 255U, 255U, 255U,
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255U, 255U, 26U, 27U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U, 255U,
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255U, 255U, 255U, 255U, 255U, 31U, 255U, 255U, 255U, 255U, 0U, 255U, 32U,
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30U, 255U, 1U, 255U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 9U,
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};
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static int pinctrl_configure_pin(pinctrl_soc_pin_t pincfg)
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{
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uint8_t pin;
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pin = (pincfg >> TI_CC32XX_PIN_POS) & TI_CC32XX_PIN_MSK;
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if ((pin >= ARRAY_SIZE(pin2pad)) || (pin2pad[pin] == 255U)) {
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return -EINVAL;
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}
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sys_write32(pincfg & MEM_GPIO_PAD_CONFIG_MSK, DT_INST_REG_ADDR(0) + (pin2pad[pin] << 2U));
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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int ret;
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ret = pinctrl_configure_pin(pins[i]);
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if (ret < 0) {
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return ret;
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}
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}
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return 0;
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}
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