50 lines
649 B
Plaintext
50 lines
649 B
Plaintext
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/*
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* Copyright (c) 2019 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <mem.h>
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#define DT_FLASH_SIZE DT_SIZE_K(8192)
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#define DT_SRAM_SIZE DT_SIZE_K(8192)
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#include <ia32.dtsi>
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/ {
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model = "ACRN";
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compatible = "intel,ia32";
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aliases {
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uart-0 = &uart0;
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uart-1 = &uart1;
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};
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chosen {
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zephyr,sram = &sram0;
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zephyr,flash = &flash0;
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zephyr,console = &uart0;
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zephyr,shell-uart = &uart0;
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};
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};
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&uart0 {
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status = "ok";
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current-speed = <115200>;
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};
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&uart1 {
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status = "ok";
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current-speed = <115200>;
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};
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&flash0 {
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reg = <0x100000 DT_FLASH_SIZE>;
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};
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&sram0 {
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reg = <0x400000 DT_SRAM_SIZE>;
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};
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