117 lines
3.9 KiB
C
117 lines
3.9 KiB
C
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/*
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* Copyright (c) 2021 Andrés Manelli <am@toroid.io>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/** @file
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* @brief System module to support early STM32 MCU configuration
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <soc.h>
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#include <zephyr/arch/cpu.h>
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#include <stm32_ll_system.h>
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#include <stm32_ll_bus.h>
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/**
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* @brief Perform SoC configuration at boot.
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*
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* This should be run early during the boot process but after basic hardware
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* initialization is done.
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*
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* @return 0
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*/
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static int st_stm32_common_config(void)
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{
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#ifdef CONFIG_LOG_BACKEND_SWO
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/* Enable SWO trace asynchronous mode */
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#if defined(CONFIG_SOC_SERIES_STM32WBX) || defined(CONFIG_SOC_SERIES_STM32H5X)
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LL_DBGMCU_EnableTraceClock();
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#endif
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#if !defined(CONFIG_SOC_SERIES_STM32WBX)
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LL_DBGMCU_SetTracePinAssignment(LL_DBGMCU_TRACE_ASYNCH);
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#endif
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#endif /* CONFIG_LOG_BACKEND_SWO */
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#if defined(CONFIG_USE_SEGGER_RTT)
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/* On some STM32 boards, for unclear reason,
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* RTT feature is working with realtime update only when
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* - one of the DMA is clocked.
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* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
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*/
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#if defined(__HAL_RCC_DMA1_CLK_ENABLE)
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__HAL_RCC_DMA1_CLK_ENABLE();
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#elif defined(__HAL_RCC_GPDMA1_CLK_ENABLE)
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__HAL_RCC_GPDMA1_CLK_ENABLE();
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#endif /* __HAL_RCC_DMA1_CLK_ENABLE */
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/* On some STM32 boards, for unclear reason,
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* RTT feature is working with realtime update only when
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* - one of the DBGMCU bit STOP/STANDBY/SLEEP is set
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* See https://github.com/zephyrproject-rtos/zephyr/issues/34324
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*/
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#if defined(LL_APB1_GRP1_PERIPH_DBGMCU)
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
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#elif defined(LL_APB1_GRP2_PERIPH_DBGMCU)
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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#elif defined(LL_APB2_GRP1_PERIPH_DBGMCU)
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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#endif /* LL_APB1_GRP1_PERIPH_DBGMCU */
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#endif /* CONFIG_USE_SEGGER_RTT */
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#if defined(CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP)
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#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X)
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HAL_EnableDBGStopMode();
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#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
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#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X)
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
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LL_DBGMCU_EnableDBGStopMode();
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
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#elif defined(SOC_SERIES_STM32F0X)
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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LL_DBGMCU_EnableDBGStopMode();
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LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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#elif defined(SOC_SERIES_STM32L0X)
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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LL_DBGMCU_EnableDBGStopMode();
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LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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#else /* all other parts */
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LL_DBGMCU_EnableDBGStopMode();
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#endif
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#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
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#else
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/* keeping in mind that debugging draws a lot of power we explcitly disable when not needed */
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#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32MP1X)
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HAL_DisableDBGStopMode();
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#else /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
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#if defined(SOC_SERIES_STM32G0X) || defined(SOC_SERIES_STM32C0X)
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
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LL_DBGMCU_DisableDBGStopMode();
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LL_APB1_GRP1_DisableClock(LL_APB1_GRP1_PERIPH_DBGMCU);
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#elif defined(SOC_SERIES_STM32F0X)
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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LL_DBGMCU_DisableDBGStopMode();
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LL_APB1_GRP2_DisableClock(LL_APB1_GRP2_PERIPH_DBGMCU);
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#elif defined(SOC_SERIES_STM32L0X)
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LL_APB2_GRP1_EnableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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LL_DBGMCU_DisableDBGStopMode();
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LL_APB2_GRP1_DisableClock(LL_APB2_GRP1_PERIPH_DBGMCU);
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#else /* all other parts */
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LL_DBGMCU_DisableDBGStopMode();
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#endif
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#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32MP1X */
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#endif /* CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP */
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return 0;
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}
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SYS_INIT(st_stm32_common_config, PRE_KERNEL_1, 1);
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