60 lines
1.1 KiB
C
60 lines
1.1 KiB
C
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/* cache.c - d-cache support for AARCH64 CPUs */
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/*
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* Copyright 2020 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief d-cache manipulation
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*
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* This module contains functions for manipulation of the d-cache.
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*/
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#include <cache.h>
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#define CTR_EL0_DMINLINE_SHIFT 16
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#define CTR_EL0_DMINLINE_MASK GENMASK(19, 16)
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#define CTR_EL0_CWG_SHIFT 24
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#define CTR_EL0_CWG_MASK GENMASK(27, 24)
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int arch_dcache_flush(void *addr, size_t size);
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int arch_dcache_invd(void *addr, size_t size);
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static size_t dcache_line_size;
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int arch_dcache_range(void *addr, size_t size, int op)
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{
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if (op == K_CACHE_INVD) {
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arch_dcache_invd(addr, size);
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} else if (op == K_CACHE_WB_INVD) {
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arch_dcache_flush(addr, size);
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} else {
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return -ENOTSUP;
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}
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return 0;
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}
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size_t arch_dcache_line_size_get(void)
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{
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uint64_t ctr_el0;
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uint32_t cwg;
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uint32_t dminline;
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if (dcache_line_size)
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return dcache_line_size;
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ctr_el0 = read_sysreg(CTR_EL0);
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cwg = (ctr_el0 & CTR_EL0_CWG_MASK) >> CTR_EL0_CWG_SHIFT;
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dminline = (ctr_el0 & CTR_EL0_DMINLINE_MASK) >>
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CTR_EL0_DMINLINE_SHIFT;
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dcache_line_size = cwg ? 4 << cwg : 4 << dminline;
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return dcache_line_size;
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}
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